MTC-20144TQ-I AMI Semiconductor, Inc., MTC-20144TQ-I Datasheet - Page 19

• Manufacturer Part Number: MTC-20144TQ-I
• Description: Integrated ADSL CMOS Analog Front-End Circuit
• Manufacturer: AMI Semiconductor, Inc.

TX / TXE Signal Dynamic
The dynamic of the signal for both
DACs is 12 bits extracted from the
available signed 16 bit representation
coming from the digital processor.
RX Signal Dynamic Range
The dynamic range of the signal from
the ADC is limited to 13 bits. Those bits
are converted to a signed representation
Control Interface Timing
The word clock (CLWD) is used to
sample at negative going edges the
control informations. The start bit b15 is
Receive / Transmit Interface
Receive / Transmit Protocol
The digital interface is based on a 4 *
8.832 MHz (35.328 MHz) clock.
The 8.832MHz 12 bits A/D output
signal or D/A input signal are SIPO
multiplexed over 4 parallel 35.328
MHz data lines in the following table.
If OSR=2 bit is selected, CLKNIB is used
as nibble clock (17.664 MHz, disabled
in normal mode), and all the RXi, TXi,
CLKWD periods are twice as long as in
normal mode. This ensure with lower
frequencies digital chips.
Fig. 11: Control Interface Timing
Fig.12: TX/TXE Bit Map
Fig.13: RX Bit Map
transmitted first followed by b[14:0] and
at least 16 stop bits need to be provided
to validate the data.
The maximal positive number is 2 14 -1,
the most negative number is -2 14 , the 3
LSBs are ignored. Any signal exceeding
these limits is clamped to the maximal
value.
with a maximal positive number of
2 14 -1 and a most negative number of
2 14 . The 2 LSBs are filled with ’0’.
RXD0 / TXD0 will contain
RXD1 / TXD1 will contain
RXD2 / TXD2 will contain
RXD3 / TXD3 will contain
19
N0
b0
b1
b2
b3
Data set up and hold time versus falling
edge CLWD > 10nsec.
MTC-20144
N1
b4
b5
b6
b7
N2 N3
b8
b9
b10 b14
b11 b15
b12
b13