MTC-20144TQ-I AMI Semiconductor, Inc., MTC-20144TQ-I Datasheet - Page 17

• Manufacturer Part Number: MTC-20144TQ-I
• Description: Integrated ADSL CMOS Analog Front-End Circuit
• Manufacturer: AMI Semiconductor, Inc.

Digital Interface
Control Interface
The digital code setting for the MTC-
20144 configuration is sent over a
serial line (CTRLIN) using the word clock
(CLWD). The data burst is composed of
16 bits from which the first bit is used as
start bit (’0’), the three LSBs being used
to identify the data contained in the 12
remaining bits. Test related data are
latched but they are overuled by the
normal settings if the TEST pin is low.
Control Interface Bit Mapping
CTRLIN[2:0]
WARNING
”000”
”001”
”010”
Description
RX settings
2 bit for external attenuation control (GC1, GC0)
1 bit for RX input selection (”0”=IN0 .. ”1”=IN1)
5 bits for AGC RX - MSB first (”00000” = 0 dB, ”11111” = 31 dB)
2 bits to force an HC filter selection for RX path
used in LT configuration to use an HC filter as RX filter
overloaded when test is active (direct selection)
”00” & ”11”
”01”
”10”
reset value = ”00”
TX settings
4 bits for AGC TX - MSB first (”0000” = -15 dB, ”1111” = 0 dB)
4 bit for AGC TXE - MSB first (”0000” = -15 dB, ”1111” = 0 dB)
3 general purpose pins (GP2, GP1, GP0)
ADSLC configuration
1 bit for digital loopback (’1’ enabled)
1 bit for analog loopback (’1’ enabled)
1 bit for VCO DAC enable (’1’ enabled)
Reserved
1 bit for OSR (’0’=4, ’1’=2)
reset value = 00b
reset value = 0b
reset value = 00000b
reset value = 0000b
reset value = 0000b
reset value = 000b
reset value = 0b
reset value = 1b
reset value = 1b
reset value = 0b
normal mode
HC2 -> RX, AGND -> TX,
HC1 -> RX, AGND -> TXE
power up HC1 if Echo not enabled !
17
MTC-20144
Bits mapping
b[14:13]
b[12]
b[11:7]
b[14:11]
b[10:7]
b[6:4]
b[14]
b[13]
b[12]
b[11]
b[10]
b[6:5]