IDT72V2113L6PF IDT, Integrated Device Technology Inc, IDT72V2113L6PF Datasheet - Page 39
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IDT72V2113L6PF
Manufacturer Part Number
IDT72V2113L6PF
Description
IC FIFO SUPERSYNCII 6NS 80-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V2103L15PF8.pdf
(46 pages)
Specifications of IDT72V2113L6PF
Function
Synchronous
Memory Size
4.7Mb (262k x 18)
Access Time
4ns
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Rate
-
Other names
72V2113L6PF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V2113L6PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V2113L6PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V2113L6PFG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
signals of multiple devices. Status flags can be detected from any one
device. The exceptions are the EF and FF functions in IDT Standard mode
and the IR and OR functions in FWFT mode. Because of variations in skew
between RCLK and WCLK, it is possible for EF/FF deassertion and IR/OR
assertion to vary by one cycle between FIFOs. In IDT Standard mode, such
problems can be avoided by creating composite flags, that is, ANDing EF
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
Word width may be increased simply by connecting together the control
GATE
FIRST WORD FALL THROUGH/
(1
)
DATA IN
SERIAL INPUT (FWFT/SI)
MASTER RESET (MRS)
FULL FLAG/INPUT READY (FF/IR) #1
PARTIAL RESET (PRS)
FULL FLAG/INPUT READY (FF/IR) #2
RETRANSMIT (RT)
m + n
PROGRAMMABLE (PAF)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
HALF-FULL FLAG (HF)
For both x9 Input and x9 Output bus Widths: 262,144 x 18 and 524,288 x 18
For the x18 Input or x18 Output bus Width: 131,072 x 36 and 262,144 x 36
D
0
- Dm
LOAD (LD)
m
Figure 29. Block Diagram of Width Expansion
72V2103
72V2113
FIFO
IDT
#1
TM
NARROW BUS FIFO
Dm
m
+1
TM
Q
- Dn
39
n
NARROW BUS FIFO
0
- Qm
of every FIFO, and separately ANDing FF of every FIFO. In FWFT mode,
composite flags can be created by ORing OR of every FIFO, and separately
ORing IR of every FIFO.
72V2113 devices. If x18 Input or x18 Output bus Width is selected, D
each device form a 36-bit wide input bus and Q
a 36-bit wide output bus. If both x9 Input and x9 Output bus Widths are selected,
D
device form an 18-bit wide output bus. Any word width can be attained by adding
additional IDT72V2103/72V2113 devices.
0
-D
Figure 29 demonstrates a width expansion using two IDT72V2103/
72V2103
72V2113
8
FIFO
IDT
from each device form an 18-bit wide input bus and Q
#2
n
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
EMPTY FLAG/OUTPUT READY (EF/OR) #2
EMPTY FLAG/OUTPUT READY (EF/OR) #1
PROGRAMMABLE (PAE)
Qm
+1
- Qn
m + n
COMMERCIAL AND INDUSTRIAL
0
-Q
TEMPERATURE RANGES
DATA
OUT
17
from each device form
6119 drw32
JUNE 1, 2010
0
-Q
8
GATE
0
from each
-D
(1
)
17
from