MT90823AG Zarlink Semiconductor, Inc., MT90823AG Datasheet - Page 7

• Manufacturer Part Number: MT90823AG
• Description: Switch Fabric, 131.072Mbps Switching Bandwidth, 3.3V Supply Voltage, 120-PBGA
• Manufacturer: Zarlink Semiconductor, Inc.

Device Overview
The MT90823 Large Digital Switch is capable of
switching up to 2,048 × 2,048 channels. The
MT90823 is designed to switch 64 kb/s PCM or N x
64 kb/s data. The device maintains frame integrity in
data applications and minimum throughput delay for
voice applications on a per channel basis.
The serial input streams of the MT90823 can have a
bit rate of 2.048, 4.096 or 8.192 Mbit/s and are
arranged in 125 µ s wide frames, which contain 32, 64
or 128 channels, respectively. The data rates on
input and output streams are identical.
By using Zarlink’s message mode capability, the
microprocessor
time-slots on a per channel basis. This feature is
useful for transferring control and status information
for external circuits or other ST-BUS devices. The
MT90823 automatically identifies the polarity of the
frame synchronization input signal and configures its
serial streams to be compatible to either ST-BUS or
GCI formats.
Two different microprocessor bus interfaces can be
selected
Non-multiplexed or Multiplexed. These interfaces
provide compatibility with multiplexed and Motorola
multiplexed/non-multiplexed buses.
The frame offset calibration function allows users to
measure the frame offset delay using a frame
evaluation pin (FE). The input offset delay can be
programmed for individual streams using internal
frame input offset registers, see Table 11.
The internal loopback allows the ST-BUS output data
to be looped around to the ST-BUS inputs for
diagnostic purposes.
Pin Description (continued)
PLCC
84
-
MQFP
1 - 4,
27 -
51 -
77 -
100
30,
54
80
through
LQFP
can
1 - 2,
24 -
49 -
74 -
99 -
100
100
27,
52,
77,
Pin #
the
access
Input
BGA
120
input
Mode
and
pin
Name
output
NC
(IM):
No connection.
Functional Description
A functional Block Diagram of the MT90823 is shown
in Figure 1.
Data and Connection Memory
For all data rates, the received serial data is
converted
serial-to-parallel converters and stored sequentially
in the data memory. Depending upon the selected
operation programmed in the interface mode select
(IMS) register, the useable data memory may be as
large as 2,048 bytes. The sequential addressing of
the data memory is performed by an internal counter,
which is reset by the input 8 kHz frame pulse (F0i) to
mark the frame boundaries of the incoming serial
data streams.
Data to be output on the serial streams may come
from either the data memory or connection memory.
Locations in the connection memory are associated
with particular ST-BUS output channels. When a
channel is due to be transmitted on an ST-BUS
output, the data for this channel can be switched
either from an ST-BUS input in connection mode, or
from the lower half of the connection memory in
message mode. Data destined for a particular
channel on a serial output stream is read from the
data memory or connection memory during the
previous channel time-slot. This allows enough time
for memory access and parallel-to-serial conversion.
Connection and Message Modes
In the connection mode, the addresses of the input
source data for all output channels are stored in the
connection memory. The connection memory is
mapped
corresponds to an output channel on the output
in
to
such
parallel
Description
a
CMOS
way
format
that
MT90823
each
by
location
internal
7