MT90823AG Zarlink Semiconductor, Inc., MT90823AG Datasheet - Page 15

• Manufacturer Part Number: MT90823AG
• Description: Switch Fabric, 131.072Mbps Switching Bandwidth, 3.3V Supply Voltage, 120-PBGA
• Manufacturer: Zarlink Semiconductor, Inc.

15 - 13
10 - 0
Bit
12
11
15
0
ST-BUS Frame
Read Address:
Reset Value:
Offset Value
Offset Value
GCI Frame
FE Input
FE Input
14
0
CLK
CLK
FD10-0
Unused
Name
FD11
CFE
13
0
CFE
Figure 4 - Example for Frame Alignment Measurement
12
Table 10 - Frame Alignment (FAR) Register Bits
FD11
11
Must be zero for normal operation.
Complete Frame Evaluation. When CFE = 1, the frame evaluation is
completed and bits FD10 to FD0 bits contains a valid frame alignment offset.
This bit is reset to zero, when SFE bit in the IMS register is changed from 1 to
0.
Frame Delay Bit 11. The falling edge of FE (or rising edge for GCI mode) is
sampled during the CLK-high phase (FD11 = 1) or during the CLK-low phase
(FD11 = 0). This bit allows the measurement resolution to 1/2 CLK cycle.
Frame Delay Bits. The binary value expressed in these bits refers to the
measured input offset value. These bits are reset to zero when the SFE bit of
the IMS register changes from 1 to 0. (FD10 = MSB, FD0 = LSB)
0
0
02
0000
H
FD10
1
10
1
,
H
.
2
2
FD9
9
3
3
4
FD8
4
8
5
5
(FD[10:0] = 06
(FD11 = 0, sample at CLK low phase)
FD7
7
6
6
7
7
FD6
6
Description
8
H
(FD[10:0] = 09
(FD11 = 1, sample at CLK high phase)
8
)
FD5
9
5
9
10
10
FD4
4
11 12
H
11 12
)
CMOS
FD3
3
13
13
FD2
14
2
14
15
15
MT90823
FD1
1
16
FD0
0
15