MT9074AL Zarlink Semiconductor, Inc., MT9074AL Datasheet - Page 32

• Manufacturer Part Number: MT9074AL
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Zarlink Semiconductor, Inc.

MT9074
32
candidates exist after a 24 bit history timeout period,
the framer forces the receive side timebase to
synchronize to the next incoming valid candidate bit
position. In the event of a reframe, the framer starts
searching at the next bit position over. This prevents
persistent locking to a mimic as the controller may
initiate a software controlled reframe in the event of
locking to a mimic.
Under software control the framing criteria may be
tuned (see Framing Mode Select Register, page 1H,
address 10H). Selecting D4 framing invites a further
decision whether or not to include a cross check of
Fs bits along with the Ft bits. If Fs bits are checked
(by setting control bit CXC high - bit 5 of the Framing
Mode Select Word, page 1H, address 10H),
multiframer alignment is forced at the same time as
terminal frame alignment. If only Ft bits are checked,
multiframe alignment is forced separately, upon
detection of the Fs bit history of 00111 (for normal D4
trunks) or 000111000111 (for SLC-96 trunks). For D4
trunks, a reframe on the multiframe alignment may
be forced at any time without affecting terminal frame
alignment.
In ESF mode, the circuit will optionally confirm the
CRC-6 bits before forcing a new frame alignment.
This is programmed by setting control bit CXC high
(bit 5 of the Framing Mode Select Word, page 1H,
address 10H). A CRC-6 confirmation adds a
minimum of 6 milliseconds to the reframe time. If no
CRC-6 match is found after 16 attempts, the framer
moves to the next valid candidate bit position
(assuming other bit positions contain a match to the
framing pattern) or re-initiates the whole framing
procedure (assuming no bit positions have been
found to match the framing pattern).
The framing circuit is off - line. During a reframe, the
rest of the circuit operates synchronous with the last
frame alignment. Until such time as a new frame
alignment is achieved, the signaling bits are frozen in
their states at the time that frame alignment was lost,
and error counting for Ft, Fs, ESF framing pattern or
CRC-6 bits is suspended.
Frame Alignment in E1 Mode
In E1 mode, MT9074 contains three distinct framing
algorithms:
multiframe
alignment. Figure 17 is a state diagram that
illustrates these algorithms and how they interact.
After power-up, the basic frame alignment framer will
search for a frame alignment signal (FAS) in the
PCM30 receive bit stream. Once the FAS is
alignment
basic
frame
and
alignment,
CRC-4
multiframe
signaling
detected, the corresponding bit 2 of the non-frame
alignment signal (NFAS) is checked. If bit 2 of the
NFAS is zero a new search for basic frame alignment
is initiated. If bit 2 of the NFAS is one and the next
FAS is correct, the algorithm declares that basic
frame synchronization has been found (i.e., page
03H, address 10H, bit 7, SYNC is zero).
Once basic frame alignment is acquired the signaling
and CRC-4 multiframe searches will be initiated. The
signaling multiframe algorithm will align to the first
multiframe alignment signal pattern (MFAS = 0000) it
receives in the most significant nibble of channel 16
(page 3, address 10H, bit 6, MFSYNC = 0). Signaling
multiframing will be lost when two consecutive
multiframes are received in error.
The CRC-4 multiframe alignment signal is a 001011
bit sequence that appears in PCM30 bit position one
of the NFAS in frames 1, 3, 5, 7, 9 and 11 (see Table
9). In order to achieved CRC-4 synchronization two
consecutive CRC-4 multiframe alignment signals
must be received without error (page 03H, address
10H CRCSYN = 0).
The E1 framing algorithm supports automatic
interworking of interfaces with and without CRC-4
processing capabilities. That is, if an interface with
CRC-4
alignment, but does not achieve CRC-4 multiframe
alignment by the end of a predefined period, the
distant end is considered to be a non-CRC-4
interface. When the distant end is a non-CRC-4
interface, the near end automatically suspends
receive CRC-4 functions, continues to transmit CRC-
4 data to the distant end with its E-bits set to zero,
and provides a status indication. Naturally, if the
distant end initially achieves CRC-4 synchronization,
CRC-4 processing will be carried out by both ends.
This feature is selected when control bit AUTC (page
01H, address 10H) is set to zero.
Notes for Synchronization State Diagram
(Figure 15)
1) The basic frame alignment, signaling multiframe
alignment,
functions operate in parallel and are independent.
2) The receive channel associated signaling bits and
signaling multiframe alignment bit will be frozen
when multiframe alignment is lost.
3) Manual re-framing of the receive basic frame
alignment and signaling multiframe alignment functi-
ons can be performed at any time.
capability, achieves
and
CRC-4
multiframe
valid
Data Sheet
basic
alignment
frame