MT9074AL Zarlink Semiconductor, Inc., MT9074AL Datasheet - Page 25

• Manufacturer Part Number: MT9074AL
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Zarlink Semiconductor, Inc.

Data Sheet
provided. Each HDLC controller has a 128 byte deep
FIFO associated with it. The status and interrupt
flags are programmable for FIFO depths that can
vary from 16 to 128 bytes in steps of 16 bytes. These
and other features are enabled through the HDLC
control registers on page 0BH and 0CH.
HDLC Frame structure
In T1 mode or E1 mode, a valid HDLC frame begins
with an opening flag, contains at least 16 bits of
address and control or information, and ends with a
16 bit FCS followed by a closing flag. Data formatted
in this manner is also referred to as a “packet”. Refer
to Table 17: HDLC Frame Format
All HDLC frames start and end with a unique flag
sequence “01111110”. The transmitter generates
these flags and appends them to the packet to be
transmitted. The receiver searches the incoming
data stream for the flags on a bit- by-bit basis to
establish frame synchronization.
The data field consists of an address field, control
field and information field. The address field consists
of one or two bytes directly following the opening
flag. The control field consists of one byte directly
following the address field. The information field
immediately follows the control field and consists of
N bytes of data. The HDLC does not distinguish
between the control and information fields and a
packet does not need to contain an information field
to be valid.
The FCS field, which precedes the closing flag,
consists of two bytes. A cyclic redundancy check
utilizing
polynomial “X
FCS. In the transmitter the FCS is calculated on all
bits of the address and data field. The complement of
the FCS is transmitted, most significant bit first, in
the FCS field. The receiver calculates the FCS on
the incoming packet address, data and FCS field and
compares the result to “F0B8”. If no transmission
errors are detected and the packet between the flags
is at least 32 bits in length then the address and data
are entered into the receive FIFO minus the FCS
which is discarded.
Flag (7E)
One Byte
01111110
Table 17 - HDLC Frame Format
the
16
CRC-CCITT
Data Field
+X
n Bytes
n
12
≥
+X
2
5
+1” produces the 16-bit
Bytes
standard
FCS
Two
Flag (7E)
One Byte
01111110
generator
Data Transparency (Zero Insertion/Deletion)
Transparency ensures that the contents of a data
packet do not imitate a flag, go-ahead, frame abort
or idle channel. The contents of a transmitted frame,
between the flags, is examined on a bit-by-bit basis
and a 0 bit is inserted after all sequences of 5
contiguous 1 bits (including the last five bits of the
FCS). Upon receiving five contiguous 1s within a
frame the receiver deletes the following 0 bit.
Invalid Frames
A frame is invalid if one of the following four
conditions exists (Inserted zeros are not part of a
valid count):
•
•
•
•
Frame Abort
The transmitter will abort a current packet by
substituting a zero followed by seven contiguous 1s
in place of the normal packet. The receiver will abort
upon reception of seven contiguous 1s occurring
between the flags of a packet which contains at least
26 bits.
Note that should the last received byte before the
frame abort end with contiguous 1s, these are
included in the seven 1s required for a receiver
abort. This means that the location of the abort
sequence in the receiver may occur before the
location of the abort sequence in the originally
transmitted packet. If this happens then the last data
written to the receive FIFO will not correspond
exactly with the last byte sent before the frame abort.
If the FCS pattern generated from the received
data does not match the “F0B8” pattern then
the last data byte of the packet is written to the
received FIFO with a ‘bad packet’ indication.
A short frame exists if there are less than 25
bits between the flags. Short frames are
ignored by the receiver and nothing is written to
the receive FIFO.
Packets which are at least 25 bits in length but
less than 32 bits between the flags are also
invalid. In this case the data is written to the
FIFO but the last byte is tagged with a “bad
packet” indication.
If a frame abort sequence is detected the
packet is invalid. Some or all of the current
packet will reside in the receive FIFO,
assuming the packet length before the abort
sequence was at least 26 bits long.
MT9074
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