MT9074AL Zarlink Semiconductor, Inc., MT9074AL Datasheet - Page 24

• Manufacturer Part Number: MT9074AL
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Zarlink Semiconductor, Inc.

MT9074
24
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External Data Link
In T1 mode MT9074 has two pairs of pins (TxDL and
TxDLCLK, RxDL and RxDLCLK) dedicated to
transmitting and receiving bits in the selected
overhead bit positions. Pins TxDLCLK and RxDLCLK
are clock outputs available for clocking data into the
MT9074 (for transmit) or external device (for receive
information). Each clock operates at 4 Khz. In the
SLC-96 mode the optional serial data link is
multiplexed into the Fs bit position. In the ESF mode
the serial data link is multiplexed into odd frames, i.e.
the FDL bit positions.
Bit - Oriented Messaging
In T1 mode MT9074 Bit oriented messaging may be
selected by setting bit 6 (BIOMEn) in the Data Link
Control Word (page 1H, address 12H). The transmit
data link will contain the repeating serial data stream
111111110xxxxxx0
originates from the user programmed register
"Transmit Bit Oriented Message" - page 1H address
13H. The receive BIOM register "Receive Bit
Oriented Message" - page 3H, address 15H, will
contain the last received valid message (the
0xxxxxx0 portion of the incoming serial bit stream).
To prevent spurious inputs from creating false
messages, a new message must be present in 7 of
the last 10 appropriate byte positions before being
loaded into the receive BIOM register. When a new
message has been received, a maskable interrupt
(maskable by setting bit 1 low in Interrupt Mask Word
Three - page 1H, address 1EH) may occur.
Dual HDLC
MT9074 has two embedded HDLC controllers
(HDLC0, HDLC1) each of which includes the
following features:
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Word. Bit - oriented messages may be
periodically interrupted (up to once per second)
for a duration of up to 100 milliseconds. This is
to accommodate bursts of message - oriented
protocols. See Table 16 for message structure.
An internal HDLC controller may be attached to
the data link.
Independent transmit and receive FIFO's;
Receive FIFO maskable interrupts for nearly full
(programmable interrupt levels) and overflow
conditions;
Transmit FIFO maskable interrupts for nearly
empty (programmable interrupt levels) and
underflow conditions;
where
the
byte
0xxxxxx0
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HLDC0 Functions
In T1 mode, ESF Data Link (DL) can be connected to
internal HDLC0, operating at a bit rate of 4 kbits/sec.
HDLC0 can be activated by setting the control bit 5,
address 12H in Master Control Page 0. Interrupts
from HDLC0 are masked when it is disconnected.
In E1 mode, when connected to the Data Link (DL)
HDLC0 will operate at a selected bit rate of 4, 8, 12,
16 or 20 kbits/sec. HDLC0 can be selected by setting
the control bit HDLC0 (page 01H, address 12H).
When this bit is zero all interrupts from HDLC0 are
masked. For more information refer to following
sections.
HDLC1 Functions
In T1 mode, DS1 channel 24 can be connected to
HDLC1, operating at 56 or 64 Kb/s. HDLC1 can be
activated by setting the control bit HDLC1 (page
01H, address 12H). Setting control bit H1R64
(address 12 H on page 01H) high selects 64 Kb/s
operation for HDLC1. Setting this bit low selects 56
Kb/s for HDLC1. Interrupts from HDLC1 are masked
when it is disconnected.
In E1 mode, this controller may be connected to time
slot 16 under Common Channel Signaling (CCS)
mode. It should be noted that the AIS16S function
will always be active and the TAIS16 (page 01H,
address 11h) function will override all other transmit
signaling.
HDLC1 can be selected by setting the control bit
HDLC1. When this bit is zero all interrupts from
HDLC1 are masked.
HDLC Description
The HDLC handles the bit oriented packetized data
transmission as per X.25 level two protocol defined
by ITU-T. It provides flag and abort sequence
generation
deletion,
generation and detection. A single byte, dual byte
and all call address in the received frame can be
recognized. Access to the receive FCS and inhibiting
of transmit FCS for terminal adaptation are also
Maskable interrupts for transmit end-of-packet
and receive end-of-packet;
Maskable interrupts for receive bad-frame
(includes frame abort);
Transmit end-of-packet and frame-abort
functions.
and
and
Frame
detection,
Check
zero
Sequence
Data Sheet
insertion
(FCS)
and