SPFD54124B Drise, SPFD54124B Datasheet - Page 197

• Manufacturer Part Number: SPFD54124B
• Description: 396-Channel 6-Bit Source Driver
• Manufacturer: Drise

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7.13.3. Reset Timing
Table 7.13.3.1 Reset input timing
Note 1) Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the table below.
Note 2. During the resetting period, the display will be blanked (The display is entering blanking sequence, which maximum time is 120 ms,
Note 3. During Reset Complete Time, ID2 and VCOMOF value in OTP will be latched to internal register during this period. This loading is
Note 4. Spike Rejection also applies during a valid reset pulse as shown below:
Note 5. It is necessary to wait 5msec after releasing RESX before sending commands. Also Sleep Out command cannot be sent for
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VSS=0V, VDDIO=1.6V to 3.6V, VDD=2.6V to 3.6V,Ta = -30 to 70 ° C)
!RES
Internal Status
RESX
Symbol
t
t
RESW
REST
when Reset Starts in Sleep Out –mode. The display remains the blank state in Sleep In –mode) and then return to Default condition
for H/W reset.
done every time when there is H/W reset complete time (tREST) within 5ms after a rising edge of RESX.
120msec.
*1) Reset low pulse width
*2) Reset complete time
Between 5 µ s and 10 µ s
Longer than 10 µ s
Shorter than 5 µ s
RESX Pulse
Shorter than 5µs
Parameter
Normal Operation
10 µ s
10µs
Related Pins
RESX
t
RESW
-
-
(It depends on voltage and temperature condition.)
Reset is accepted
197
MIN
10
-
Resetting
t
REST
TYP
Reset Rejected
-
-
-
Reset starts
Action
Reset
MAX
120
5
-
(Default for H/W reset)
When reset applied during
When reset applied during
Initial Condition
Sleep out mode
Sleep in mode
Note
SPFD54124B
-
Preliminary
Preliminary Version: 0.6
APR. 26, 2007
Unit
ms
ms
µ s