SPFD54124B Drise, SPFD54124B Datasheet - Page 146

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SPFD54124B

Manufacturer Part Number
SPFD54124B
Description
396-Channel 6-Bit Source Driver
Manufacturer
Drise
Datasheet
www.DataSheet4U.com
7.4.4.
All 4-kinds of bus width can be available during RGB interface mode (selected by COLMOD (3Ah) command for 8-bits, 16-bits and 18-bits
data width)
Table 7.4.4.1 RGB interface Bus Width Set Table
Note 1: When VIPF[3:0]=”1110”, 6-bits data width of 3-times transfer is used to transmit 1 pixel data with the 18-bits color depth information.
Note 2: Only VIPF[3:0]= ”0101”,”0110” and “1110” are valid on RGB I/F, Others are invalid.
Note 3. ‘x’ Don’t care, but need to set VDDIO or DGND level.
7.4.5.
Table 7.4.5.1 RGB Interface Mode Set
There are 2-kinds of RGB mode which is selected by RCM1 & RCM0 hardware pins.
In RGB Mode 1 (RCM1, RCM0 = “10”), writing data to frame memory is done by PCLK and Video Data Bus (D[17:0]), when DE is high
state. The external synchronization signals (PCLK, VS and HS) are used for internal display signals. So, controller (host) must always
transfer PCLK, VS, HS and DE signals to SPFD54124B.
In RGB Mode 2 (RCM1, RCM0 = “11”), blanking porch setting of VS and HS signals are defined by RGBBPCTR (B5h) command. When DE
pin is high, valid data is directly stored to frame memory.
© ORISE Technology Co., Ltd.
Proprietary & Confidential
RGB I/F Mode
VIPF[3:0]
VIPF[3:0]
RGB Mode 1
RGB Mode 2
0101
0110
1110
RGB Interface Bus Width set
RGB Interface Mode Set
D17 D16 D15 D14 D13 D12 D11 D10
D17 D16 D15 D14 D13 D12 D11 D10
R4
R5
x
x
x
PCLK
Used
Used
R3
R4
x
x
x
R2
R3
x
x
x
Used
Used
DE
R1
R2
x
x
x
R0
R1
x
x
x
Used
Used
VS
R0
x
x
x
x
G5
G5
x
x
x
Used
Used
HS
G4
G4
x
x
x
Video Data bus
D9
G3
G3
D9
x
x
x
D[17:0]
146
Used
Used
D8
G2
G2
D8
x
x
x
D7
G1
G1
D7
R5
G5
B5
D6
G0
G0
D6
R4
G4
B4
Register for Blanking
G3
D5
B4
B5
D5
R3
B3
Porch setting
Not Used
Used
G2
D4
B3
B4
D4
R2
B2
G1
D3
B2
B3
D3
R1
B1
G0
D2
B1
B2
D2
R0
B0
SPFD54124B
Preliminary
D1
B0
B1
D1
Reference clock for
x
x
x
Internal Oscillator
Internal Oscillator
Preliminary Version: 0.6
D0 Bus width
B0
D0 Bus width
Display
x
x
x
x
6-bits data
APR. 26, 2007
16-bits
18-bits
data
data

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