SPFD54124B Drise, SPFD54124B Datasheet - Page 151

• Manufacturer Part Number: SPFD54124B
• Description: 396-Channel 6-Bit Source Driver
• Manufacturer: Drise

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Table 7.4.6.2.1 Vertical and Horizontal Timing for RGB I/F
Vertical Timing
Vertical cycle period
Vertical low pulse width
Vertical front porch
Vertical back porch
Vertical data start line
Vertical blanking period
Vertical active area
Vertical refresh rate
Horizontal Timing
Horizontal cycle period
Horizontal low pulse width
Horizontal front porch
Horizontal back porch
Horizontal data start point
Horizontal blanking period
Horizontal active area
Pixel clock cycle
Note 1. VDDIO=1.6 to 3.6V, VDD=2.6 to 3.6V, AGND=DGND=0V, Ta=-30 to 70
Note 2. Data lines can be set to “High” or “Low” during blanking time – Don’t care.
Note 3. HP is multiples of eight PCLK.
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Item
Symbol
T
T
T
f
f
f
TVRR
PCLKCYC
PCLKCYC
PCLKCYC
T
T
PCLKCYC
PCLKCYC
PCLKCYC
T
T
T
T
T
T
T
T
T
T
VDISP
HDISP
HBP
VFP
VBP
VBL
HFP
HBL
VP
VS
HP
HS
GM=”00” & “01”
GM=”00” & “01”
GM=”00” & “10”
GM=”00” & “10”
T
TVRR=65Hz
TVRR=65Hz
TVRR=65Hz
VS +
Frame rate
Condition
ff
GM=”10”
T
GM=”10”
GM=”01”
T
GM=”01”
GM=”00”
GM=”01”
GM=”10”
HS
HS +
VS +
T
VBP +
+ f
151
T
T
VBP
HBP
HBP
T
VFP
℃
(to +85
61.75
Min
166
134
160
152
100
100
100
1.0
1.7
1.6
1.4
30
32
2
2
2
4
6
2
2
2
℃
no damage)
Specification
Type.
160
128
128
120
65
SPFD54124B
Preliminary
68.25
Max
172
140
745
745
256
256
256
766
768
579
610
718
Preliminary Version: 0.6
12
10
10
10
4
4
4
8
APR. 26, 2007
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
MHz
MHz
MHz
Unit
HS
HS
HS
HS
HS
HS
HS
HS
Hz
µ s
ns
ns
ns