CLA80000 Zarlink Semiconductor, CLA80000 Datasheet - Page 6

• Manufacturer Part Number: CLA80000
• Description: High Density CMOS Gate Arrays
• Manufacturer: Zarlink Semiconductor

DESIGN SUPPORT
Design Route
I Flexible design route
I Proven right first time design
Design and layout support for the CLA80k arrays is
available from many centres worldwide each of which is
connected to our headquarters via high speed data links. A
design centre engineer is assigned to each customer's
circuit to ensure the best assistance, and a smooth and
efficient design flow.
Zarlink offers a variety of formal design routes as illustrated
in Figure 5. A choice of routes allow for varying levels of
customer involvement in a manner which complements
individual customers' design styles, whilst maintaining
Zarlink’s responsibility to ensure first time working devices.
The design process incorporates a design audit procedure
to verify compliance with customer specification and to
ensure manufacturability. The procedure includes four
review meetings with the customer held at key stages of the
design.
Review 1: Held at the beginning of the design cycle to
check
specifications and design timescales.
Review 2: Held after Logic Simulation but prior to layout to
ensure satisfactory functionality, timing performance, and
adequate fault coverage.
Review 3: Held after Layout and Post Layout Simulation
Verification of satisfactory design performance after
insertion of actual track loads. Final check of all device
specifications before prototype manufacture.
Review 4: Held after Prototype Delivery to confirm that
devices meet all specifications and are suitable for full scale
production.
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packaging,
CAE Support
I Synthesis with Synopsys, Mentor or Cadence
I Sign-off simulation with Mentor or Cadence
I VIEWlogic VCS simulator supported
I VITAL compliant library
I Full top-down design flow support
I Point tools supported, including Zycad and Powermill
I Direct route to layout and test
I Advanced delay modelling and netlist checking
It is Zarlink policy to fully support industry-standard CAE
systems that enable a customer to sign off their design
without resimulation on a golden simulator. This has the
benefit to the customer of not having to learn new tools, and
to use the tools they prefer and are familiar with. There is
no overhead in engineering effort or time taken rechecking
simulation results.
Zarlink offers libraries for synthesis tools such as
Synopsys, Mentor Autologic II, and Cadence Synergy. This
allows a full hierarchical or top-down approach to logic
design. The Zarlink’s Universal Delay Compiler (UDC) is
supplied with all design kits for advanced delay modelling
and comprehensive netlist checking. The UDC matches
Synopsys and Mentor native delay calculation.
The advanced features of the synthesis and simulation
tools are used for nonlinear delay modelling for better
simulation accuracy. This is implemented for optimum
speed depending on the particular tool. Other advanced
features are supported where they are available.
The information supplied by the customer in the approved
CAE vendor format is used as a direct input to the tools that
perform the layout and generate the test program.