CLA80000 Zarlink Semiconductor, CLA80000 Datasheet - Page 3

• Manufacturer Part Number: CLA80000
• Description: High Density CMOS Gate Arrays
• Manufacturer: Zarlink Semiconductor

CLOCK AND POWER DISTRIBUTION
I Low skew clock distribution strategy
I Power grid to minimize voltage drop
In large complex designs working at high speed, on chip
clock and power distribution is vital to successful operation
of the design. Zarlink has a number of techniques to
minimize potential problems which can occur with clocking
and powering the chip.
Clock Distribution
The clock distribution network must ensure that skew is
minimized and that long term failure does not occur due to
metal
ZarlinkZarlink are:
Large buffer
Balanced Tree
Clock Grid
Distributed clock buffer cells are supported for the CLA80k
family to minimise clock skew effects across a die. The use
of these cells is restricted to three layer metal designs.
Each array size from CLT84 upwards has its own unique
buffer cell (CLKB8*).
block but with the output drive distributed across the die.
The clock signal is routed at layout either as a grid, ring or
spine structure to maintain clock skew within acceptable
limits. These clock buffer cells are entered in the circuit
schematic at the top level of the and all registers and
latches should be driven directly from the clock buffer
output.
Power Distribution
The power distribution metal in the array must be designed
to avoid excessive voltage drops and long term failure due
to electromigration.
Metal 1 V
At regular intervals across the array the metal 1 supply rails
are fed by vertical metal 2 straps. For designs using three
layers of metal additional straps can be added in metal 3.
Fig 4 shows a representation of the grid arrangement.
MANUFACTURING
I Computer aided manufacturing
I Class 10 or better clean room conditions
I Vibration free for reliable manufacture
The CLA80k product is manufactured near Plymouth
England in a purpose built factory for sub-micron process
geometry. The factory uses the latest automated
equipment for 6-inch wafers in vibration free class 10 clean
room conditions. Computer Aided Manufacture in the
above environment ensures production efficiency and the
lowest possible defect level. In addition to the world class
wafer facility there are excellent probe and final test areas
equipped with the latest analog and digital testers.
migration.
DD
and V
SS
tracks pass through all the array cells.
Three
Each of the cells occupy one I/O
solutions
available
from
This
Semiconductor’s commitment to providing state-of-the-art
CMOS ASICS.
Figure 3 Example of distributed clock buffer using
Figure 4 Example of three layer metal power grid
continued
Metal 2
Vertical
Grid
investment
MACROCELL
a grid structure
Horizontal
metal 3 Grid
demonstrates
Metal 2
Vertical
Grid
Metal 3
Horizontal
Grid
RAM
Pad
Pad
Zarlink
3