CLA80000 Zarlink Semiconductor, CLA80000 Datasheet - Page 2

• Manufacturer Part Number: CLA80000
• Description: High Density CMOS Gate Arrays
• Manufacturer: Zarlink Semiconductor

ARCHITECTURE
Core cell
I Optimized structure for a variety of logic elements
I Allows routing through cells for compact layout
The basic unit from which all library functions are
constructed is called an ‘array element’. An array element
consists of two P-channel and two N-channel plus a small
P-channel transistor. Two basic cell or array elements are
illustrated in Figure 1. To achieve the required circuit
function, logic designers use a set of cells. Each library
component realizes a logic function, ranging in complexity
from an inverter to a master-slave ‘D’ flip-flop. A fixed metal
interconnection of the transistors from one or more array
elements implements the cell function. A design is
specified in terms of cells, macros, modules and their
interconnections, which are then simulated using one of the
many supported design platforms.
If a design uses only two layers of metal then a set of four
masks is required. One for contacts, one for vias
(connections between the metal layers) and two for metals.
If a design uses three layer metal then six masks are
required. One for contacts, two for vias and three for
metals.
I/O ARRANGEMENT
I High density and standard density pads available
I 4KV ESD and latchup immunity
I Programmable slew rate control
Around the outside of the array are I/O blocks and pads
placed at the chip periphery. All arrays have wide power
bus rings situated over the I/O blocks. The partition of the
I/O cell is shown in Figure 2. For high density pad arrays
three pads are placed every four I/O cells whilst for
standard density array pads two pads are placed for every
three I/O cells.
Each I/O cell is divided into a number of sections allowing
a wide variety of different I/O cells to be constructed. Each
I/O block can be customized as an input, output or bi-
directional I/O port. In addition any pad location can be
used as a positive or negative supply pad.
Electrostatic discharge protection (ESD) is built into the I/O
cells. This protection can withstand in excess of 4kV. The
structure is also highly resistant to latch-up due to the
epitaxial substrate used in the process.
Slew rate control is provided within the I/O cell structure to
minimize supply noise transients. This is a useful feature in
larger designs where multiple high drive outputs need to be
switched simultaneously.
2
IB-V
IB-GND
OP-V
OP-GND
OP-V
DD
DD
DD
Figure 2 High density pad spacing
Figure 1 Pair of array elements
Array Element
Repeated Structure
Array Element
Intermediate
Buffers
V
GND Supply
Output
Drivers
Bond
Pads
Diffusion
Shared
DD
P Trans
N Trans
Supply