MT16LSDF3264LHY-10E Micron, MT16LSDF3264LHY-10E Datasheet - Page 9

• Manufacturer Part Number: MT16LSDF3264LHY-10E
• Description: DRAM Module, 256MB, 512MB (x64, DR) 144Pin SDRAM SODIMM
• Manufacturer: Micron

Table 7:
NOTE:
pdf: 09005aef807924d2, source: 09005aef807924f1
SDF16C32_64x64HG.fm - Rev. D 9/04 EN
LENGTH
1. For full-page accesses: y = 1,024 (both 256MB and
2. For a burst length of two, A1–A9 select the block-of-
3. For a burst length of four, A2–A9 select the block-of-
4. For a burst length of eight, A3–A9 select the block-of-
5. For a full-page burst, the full row is selected and A0–A9
6. Whenever a boundary of the block is reached within a
7. For a burst length of one, A0–A9 select the unique col-
BURST
Page
Full
(y)
512MB modules)
two burst; A0 selects the starting column within the
block.
four burst; A0–A1 select the starting column within the
block.
eight burst; A0–A2 select the starting column within
the block.
select the starting column.
given sequence above, the following access wraps
within the block.
umn to be accessed, and mode register bit M3 is
ignored.
2
4
8
A2 A1 A0
STARTING
ADDRESS
n = A0-A9
COLUMN
0
0
0
0
1
1
1
1
(location
0-y)
A1 A0
0
0
1
1
0
0
1
1
0
0
1
1
Burst Definition Table
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
…Cn - 1, Cn…
SEQUENTIAL
TYPE =
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
ORDER OF ACCESSES
0-1
1-0
WITHIN A BURST
INTERLEAVED
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not supported
TYPE =
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0
9
Burst Type
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 7, Burst
Definition Table.
CAS Latency
between the registration of a READ command and the
availability of the first piece of output data. The latency
can be set to two or three clocks.
and the latency is m clocks, the data will be available
by clock edge n + m. The DQ will start driving as a
result of the clock edge one cycle earlier (n + m - 1),
and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example,
assuming that the clock cycle time is such that all rele-
vant access times are met, if a READ command is regis-
tered at T0 and the latency is programmed to two
clocks, the DQ will start driving after T1 and the data
will be valid by T2, as shown in Figure 4, Mode Register
Definition Diagram. Table 8, CAS Latency Table, on
page 10 indicates the operating frequencies at which
each CAS latency setting can be used.
COMMAND
COMMAND
Accesses within a given burst may be programmed
The ordering of accesses within a burst is deter-
The CAS latency is the delay, in clock cycles,
If a READ command is registered at clock edge n,
CLK
CLK
DQ
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Figure 5: CAS Latency Diagram
READ
READ
144-PIN SDRAM SODIMM
T0
T0
256MB, 512MB (x64, DR)
CAS Latency = 2
NOP
NOP
T1
T1
t
t AC
LZ
CAS Latency = 3
©2004 Micron Technology, Inc. All rights reserved.
T2
NOP
T2
NOP
t
t AC
LZ
D
t OH
OUT
T3
T3
NOP
D
t OH
OUT
DON’T CARE
UNDEFINED
T4