MT16LSDF3264LHY-10E Micron, MT16LSDF3264LHY-10E Datasheet - Page 8

• Manufacturer Part Number: MT16LSDF3264LHY-10E
• Description: DRAM Module, 256MB, 512MB (x64, DR) 144Pin SDRAM SODIMM
• Manufacturer: Micron

M3 specifies the type of burst (sequential or inter-
leaved), M4–M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write
burst mode, and M10 and M11 are reserved for future
use. For the 256MB and 512MB, M12 (A12) is unde-
fined, but should be driven LOW during loading of the
mode register.
banks are idle, and the controller must wait the speci-
fied time before initiating the subsequent operation.
Violating either of these requirements will result in
unspecified operation.
Burst Length
ented, with the burst length being programmable, as
shown in Figure 4, Mode Register Definition Diagram.
The burst length determines the maximum number of
column locations that can be accessed for a given
READ or WRITE command. Burst lengths of 1, 2, 4, or 8
locations are available for both the sequential and the
interleaved burst types, and a full-page burst is avail-
able for the sequential type. The full-page burst is used
in conjunction with the BURST TERMINATE com-
mand to generate arbitrary burst lengths.
operation or incompatibility with future versions may
result.
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached, as shown in Table 7,
Burst Definition Table, on page 9. The block is
uniquely selected by A1–A9 when the burst length is
set to two; by A2–A9 when the burst length is set to
four; and by A3–A9 when the burst length is set to
eight. The remaining (least significant) address bit(s) is
(are) used to select the starting location within the
block. Full-page bursts wrap within the page if the
boundary is reached, as shown in Table 7, Burst Defini-
tion Table, on page 9.
pdf: 09005aef807924d2, source: 09005aef807924f1
SDF16C32_64x64HG.fm - Rev. D 9/04 EN
Mode register bits M0–M2 specify the burst length,
The mode register must be loaded when all device
Read and write accesses to the SDRAM are burst ori-
Reserved states should not be used, as unknown
When a READ or WRITE command is issued, a block
8
256MB Module
512MB Module
M12, M11, M10 = “0, 0, 0”
to ensure compatibility
with future devices.
*Should program
Figure 4: Mode Register Definition
M11 and M10 = “0, 0, 0”
to ensure compatibility
with future devices.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
*Should program
12
A12
Reserved*
Reserved* WB
11
11
A11
A11
10
10
144-PIN SDRAM SODIMM
A10
A10
256MB, 512MB (x64, DR)
WB
M9
0
1
9
9
A9
A9
Op Mode
Op Mode
8
8
A8
A8
7
7
A7
A7
Programmed Burst Length
Diagram
M8
0
-
Single Location Access
CAS Latency
CAS Latency
6
6
Write Burst Mode
A6
A6
5
5
M7
A5
A5
0
-
4
4
A4
A4
©2004 Micron Technology, Inc. All rights reserved.
M3
BT
BT
Defined
M6-M0
0
1
3
3
A3
A3
-
M2
M6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Burst Length
Burst Length
2
2
M1
A2
A2
M5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
M0
M4
1
1
0
1
0
1
0
1
0
1
Operating Mode
Standard Operation
All other states reserved
0
1
0
1
0
1
0
1
A1
A1
0
0
A0
A0
Full Page
Reserved
Reserved
Reserved
M3 = 0
Burst Type
Interleaved
Sequential
1
2
4
8
Mode Register (Mx)
Mode Register (Mx)
Address Bus
Address Bus
Burst Length
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
M3 = 1
1
2
4
8