IDT723644L12PF IDT, Integrated Device Technology Inc, IDT723644L12PF Datasheet - Page 32
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IDT723644L12PF
Manufacturer Part Number
IDT723644L12PF
Description
IC FIFO SYNC 2048X36 128QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
7200r
Datasheet
1.IDT723624L15PF8.pdf
(35 pages)
Specifications of IDT723644L12PF
Function
Synchronous
Memory Size
72K (2K x 36)
Data Rate
83MHz
Access Time
12ns
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
723644L12PF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT723644L12PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT723644L12PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTE:
1. If Port B is configured for word size, data can be written to the Mail1 register using A0-A17 (A18-A35 are don't care inputs). In this first case B0-B17 will have valid data (B18-B35 will be
NOTES:
1. t
2. FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the IDT723624, 512 for the IDT723634, 1,024 for the IDT723644.
4. If Port B size is word or byte, AFB is set LOW by the last word or byte write of the long word, respectively.
IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
A0-A35
B0-B35
indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0-A8 (A9-A35 are don't care inputs). In this second case, B0-B8 will have valid data
(B9-B35 will be indeterminate).
and rising CLKA edge is less than t
MBF1
CLKA
CLKB
W/RA
W/RB
SKEW2
MBA
MBB
CSA
CSB
ENA
ENB
CLKB
CLKA
ENB
AFB
ENA
is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge
[D-(Y2+1)] Words in FIFO2
t
Figure 26. Timing for AFB
Figure 27. Timing for Mail1 Register and MBF1
ENS2
SKEW2
t
t
t
t
ENS1
ENS2
ENS2
ENS1
t
FIFO1 Output Register
EN
, then AFB may transition HIGH one CLKB cycle later than shown.
t
DS
t
W1
t
ENH
PAF
AFB
AFB
AFB
AFB when FIFO2 is Almost-Full (IDT Standard and FWFT Modes)
t
MDV
t
t
t
t
DH
t
ENH
ENH
ENH
ENH
t
PMF
t
ENS2
t
PMR
MBF1
MBF1
MBF1
MBF1 Flag (IDT Standard and FWFT Modes)
32
(D-Y2) Words in FIFO2
t
SKEW2
t
W1 (Remains valid in Mail1 Register after read)
ENH
(1)
1
t
ENS2
COMMERCIAL TEMPERATURE RANGE
t
ENH
t
PMF
2
t
PAF
t
DIS
3270 drw29
3270 drw28