IDT72V285L20TF IDT, Integrated Device Technology Inc, IDT72V285L20TF Datasheet - Page 24
![IC FIFO SS 65536X18 20NS 64STQFP](/photos/31/27/312736/64pin_tqfp_sml.jpg)
IDT72V285L20TF
Manufacturer Part Number
IDT72V285L20TF
Description
IC FIFO SS 65536X18 20NS 64STQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V275L15TF8.pdf
(25 pages)
Specifications of IDT72V285L20TF
Function
Asynchronous
Memory Size
1.1M (65K x 18)
Data Rate
50MHz
Access Time
20ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-STQFP
Configuration
Dual
Density
1.125Mb
Access Time (max)
12ns
Word Size
18b
Organization
64Kx18
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
STQFP
Clock Freq (max)
50MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Supply Current
60mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V285L20TF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V285L20TF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V285L20TF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
FIFO in the chain to go LOW after a word has been read from the last FIFO is
the sum of the delays for each individual FIFO:
where N is the number of FIFOs in the expansion and T
period. Note that extra cycles should be added for the possibility that the t
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO
32,768 x 18 and 65,536 x 18
FWFT/SI
WRITE ENABLE
INPUT READY
DATA IN
WRITE CLOCK
For a full expansion configuration, the amount of time it takes for IR of the first
n
(N – 1)*(3*transfer clock) + 2 T
Dn
WEN
IR
WCLK
Figure 20. Block Diagram of 65,536 x 18 and 131,072 x 18 Depth Expansion
FWFT/SI
72V275
72V285
IDT
•
TRANSFER CLOCK
WCLK
RCLK
REN
OE
TM
OR
Qn
WCLK
is the WCLK
SKEW1
•
GND
n
24
specification is not met between RCLK and transfer clock, or WCLK and transfer
clock, for the IR flag.
is faster. Both these actions result in data moving, as quickly as possible, to the
end of the chain and free locations to the beginning of the chain.
The Transfer Clock line should be tied to either WCLK or RCLK, whichever
WCLK
IR
Dn
WEN
FWFT/SI
72V275
72V285
IDT
COMMERCIAL AND INDUSTRIAL
RCLK
REN
OR
OE
Qn
TEMPERATURE RANGES
OUTPUT ENABLE
n
OUTPUT READY
READ ENABLE
READ CLOCK
DATA OUT
4512 drw 23