LM3S2918 Luminary Micro, Inc, LM3S2918 Datasheet - Page 484

• Manufacturer Part Number: LM3S2918
• Description: Lm3s2918 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Signal Tables
484
Table 19-6. Signals by Signal Name
Pin Number
M10
M12
M11
M5
M6
M7
M8
M9
Pin Name
CAN0Rx
CAN0Tx
CMOD0
CMOD1
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
CCP0
CCP1
CCP2
CCP3
CCP4
CCP5
CCP6
CCP7
C0+
C0-
C0o
C1+
C1-
C1o
Pin Name
I2C1SDA
SSI0Tx
CCP1
WAKE
OSC1
PA5
PA7
PG5
PF6
PF0
HIB
Pin Number
D12
E12
E11
B10
M1
M8
M2
B1
A1
B3
B2
A2
A3
B4
A4
A7
A6
B7
G1
G2
C9
C8
L9
L8
L2
L1
Preliminary
Pin Type
Pin Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Buffer Type
Buffer Type
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
OD
-
Description
GPIO port A bit 5
SSI module 0 transmit
GPIO port A bit 7
I2C module 1 data
GPIO port G bit 5
GPIO port F bit 6
Capture/Compare/PWM 1
GPIO port F bit 0
An external input that brings the processor out
of hibernate mode when asserted.
Main oscillator crystal output.
An output that indicates the processor is in
hibernate mode.
Description
Analog-to-digital converter input 0.
Analog-to-digital converter input 1.
Analog-to-digital converter input 2.
Analog-to-digital converter input 3.
Analog-to-digital converter input 4.
Analog-to-digital converter input 5.
Analog-to-digital converter input 6.
Analog-to-digital converter input 7.
Analog comparator 0 positive input
Analog comparator 0 negative input
Analog comparator 0 output
Analog comparator positive input
Analog comparator 1 negative input
Analog comparator 1 output
CAN module 0 receive
CAN module 0 transmit
Capture/Compare/PWM 0
Capture/Compare/PWM 1
Capture/Compare/PWM 2
Capture/Compare/PWM 3
Capture/Compare/PWM 4
Capture/Compare/PWM 5
Capture/Compare/PWM 6
Capture/Compare/PWM 7
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
July 26, 2008