LM3S2918 Luminary Micro, Inc, LM3S2918 Datasheet - Page 285

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LM3S2918

Manufacturer Part Number
LM3S2918
Description
Lm3s2918 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet

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Reset
Reset
Type
Type
ADC Sample Averaging Control (ADCSAC)
Base 0x4003.8000
Offset 0x030
Type R/W, reset 0x0000.0000
July 26, 2008
Bit/Field
31:3
2:0
RO
RO
31
15
0
0
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030
This register controls the amount of hardware averaging applied to conversion results. The final
conversion result stored in the FIFO is averaged from 2
ADC speed. If AVG is 0, the sample is passed directly through without any averaging. If AVG=6,
then 64 consecutive ADC samples are averaged to generate one result in the sequencer FIFO. An
AVG = 7 provides unpredictable results.
RO
RO
30
14
0
0
reserved
RO
RO
29
13
0
0
Name
AVG
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
R/W
RO
RO
RO
26
10
0
0
reserved
Reset
0x00
0x0
RO
RO
25
0
9
0
Preliminary
RO
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Hardware Averaging Control
Specifies the amount of hardware averaging that will be applied to ADC
samples. The AVG field can be any value between 0 and 6. Entering a
value of 7 creates unpredictable results.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
reserved
RO
RO
23
Description
No hardware oversampling
2x hardware oversampling
4x hardware oversampling
8x hardware oversampling
16x hardware oversampling
32x hardware oversampling
64x hardware oversampling
Reserved
0
7
0
AVG
RO
RO
22
0
6
0
consecutive ADC samples at the specified
RO
RO
21
0
5
0
RO
RO
20
0
4
0
LM3S2918 Microcontroller
RO
RO
19
0
3
0
R/W
RO
18
0
2
0
AVG
R/W
RO
17
0
1
0
R/W
RO
16
0
0
0
285

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