LM3S2918 Luminary Micro, Inc, LM3S2918 Datasheet - Page 392

• Manufacturer Part Number: LM3S2918
• Description: Lm3s2918 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Inter-Integrated Circuit (I
Read-Only Status Register
I2C Master Control/Status (I2CMCS)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x004
Type RO, reset 0x0000.0000
392
Bit/Field
31:7
6
5
4
RO
RO
31
15
0
0
Register 2: I
This register accesses four control bits when written, and accesses seven status bits when read.
The status register consists of seven bits, which when read determine the state of the I
controller.
The control register consists of four bits: the RUN, START, STOP, and ACK bits. The START bit causes
the generation of the START, or REPEATED START condition.
The STOP bit determines if the cycle stops at the end of the data cycle, or continues on to a burst.
To generate a single send cycle, the I
the desired address, the R/S bit is set to 0, and the Control register is written with ACK=X (0 or 1),
STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation is completed
(or aborted due an error), the interrupt pin becomes active and the data may be read from the
I2CMDR register. When the I
normally to logic 1. This causes the I
each byte. This bit must be reset when the I
from the slave transmitter.
RO
RO
30
14
0
0
BUSBSY
reserved
ARBLST
RO
RO
29
13
0
0
Name
IDLE
2
C) Interface
RO
RO
28
12
0
0
2
C Master Control/Status (I2CMCS), offset 0x004
reserved
RO
RO
27
11
0
0
Type
RO
RO
RO
RO
RO
RO
26
10
0
0
2
C module operates in Master receiver mode, the ACK bit must be set
Reset
0x00
RO
RO
25
0
9
0
0
0
0
2
Preliminary
2
C bus controller to send an acknowledge automatically after
C Master Slave Address (I2CMSA) register is written with
RO
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Bus Busy
This bit specifies the state of the I
otherwise, the bus is idle. The bit changes based on the START and
STOP conditions.
I
This bit specifies the I
otherwise the controller is not idle.
Arbitration Lost
This bit specifies the result of bus arbitration. If set, the controller lost
arbitration; otherwise, the controller won arbitration.
2
reserved
C Idle
2
C bus controller requires no further data to be sent
RO
RO
23
0
7
0
BUSBSY
RO
RO
22
0
6
0
2
C controller state. If set, the controller is idle;
IDLE
RO
RO
21
0
5
0
ARBLST
RO
RO
20
0
4
0
2
C bus. If set, the bus is busy;
DATACK
RO
RO
19
0
3
0
ADRACK
RO
RO
18
0
2
0
July 26, 2008
ERROR
2
RO
RO
17
0
1
0
C bus
BUSY
RO
RO
16
0
0
0