IDT72V283L10PFI IDT, Integrated Device Technology Inc, IDT72V283L10PFI Datasheet - Page 39
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IDT72V283L10PFI
Manufacturer Part Number
IDT72V283L10PFI
Description
IC FIFO 32768X18 10NS 80QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V293L7-5PF.pdf
(45 pages)
Specifications of IDT72V283L10PFI
Function
Asynchronous, Synchronous
Memory Size
589K (32K x 18)
Data Rate
100MHz
Access Time
10ns
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
80-TQFP, 80-VQFP
Configuration
Dual
Density
576Kb
Access Time (max)
6.5ns
Word Size
9/18Bit
Organization
32Kx18/64Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
100MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.15V
Operating Supply Voltage (max)
3.45V
Supply Current
30@9BIT/35@18BITmA
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V283L10PFI
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V283L10PFI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V283L10PFI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
signals of multiple devices. Status flags can be detected from any one
device. The exceptions are the EF and FF functions in IDT Standard mode
and the IR and OR functions in FWFT mode. Because of variations in skew
between RCLK and WCLK, it is possible for EF/FF deassertion and IR/OR
assertion to vary by one cycle between FIFOs. In IDT Standard mode, such
problems can be avoided by creating composite flags, that is, ANDing EF
of every FIFO, and separately ANDing FF of every FIFO. In FWFT mode,
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
For the x18 Input or x18 Output bus Width: 512 x 36, 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36 and 65,536 x 36
For both x9 Input and x9 Output bus Widths: 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18, 16,284 x 18, 32,768 x 18, 65,536 x 18 and 131,072 x 18
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
Word width may be increased simply by connecting together the control
GATE
FIRST WORD FALL THROUGH/
(1)
DATA IN
SERIAL INPUT (FWFT/SI)
FULL FLAG/INPUT READY (FF/IR) #1
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FULL FLAG/INPUT READY (FF/IR) #2
RETRANSMIT (RT)
m + n
PROGRAMMABLE (PAF)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
HALF-FULL FLAG (HF)
D
0
- Dm
LOAD (LD)
m
Figure 29. Block Diagram of Width Expansion
72V223
72V233
72V243
72V253
72V263
72V273
72V283
72V293
FIFO
IDT
#1
Dm
m
+1
TM
Q
- Dn
39
n
NARROW BUS FIFO
0
- Qm
composite flags can be created by ORing OR of every FIFO, and separately
ORing IR of every FIFO.
72V243/72V253/72V263/72V273/72V283/72V293 devices. If x18 Input or
x18 Output bus Width is selected, D
input bus and Q
x9 Input and x9 Output bus Widths are selected, D
an 18-bit wide input bus and Q
bus. Any word width can be attained by adding additional IDT72V223/72V233/
72V243/72V253/72V263/72V273/72V283/72V293 devices.
TM
Figure 29 demonstrates a width expansion using two IDT72V223/72V233/
NARROW BUS FIFO
72V223
72V233
72V243
72V253
72V263
72V273
72V283
72V293
FIFO
IDT
#2
0
n
-Q
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
EMPTY FLAG/OUTPUT READY (EF/OR) #2
EMPTY FLAG/OUTPUT READY (EF/OR) #1
PROGRAMMABLE (PAE)
17
Qm
from each device form a 36-bit wide output bus. If both
+1
- Qn
0
-Q
8
from each device form an 18-bit wide output
0
-D
m + n
17
COMMERCIAL AND INDUSTRIAL
from each device form a 36-bit wide
TEMPERATURE RANGES
0
DATA OUT
-D
FEBRUARY 11, 2009
8
from each device form
4666 drw32
GATE
(1)