LM3S1133 Luminary Micro, Inc, LM3S1133 Datasheet - Page 396

• Manufacturer Part Number: LM3S1133
• Description: Lm3s1133 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Inter-Integrated Circuit (I
396
a. An X in a table cell indicates the bit can be 0 or 1.
b. In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by
Current
State
Master
Receive
the master or an Address Negative Acknowledge executed by the slave.
I2CMSA[0]
All other combinations not listed are non-operations.
R/S
2
C) Interface
X
X
X
X
X
1
1
1
0
0
ACK
0
X
0
1
1
0
0
1
X
X
STOP
I2CMCS[3:0]
0
1
1
0
1
0
1
0
0
1
START
Preliminary
0
0
0
0
0
1
1
1
1
1
RUN
1
0
1
1
1
1
1
1
1
1
Description
RECEIVE operation with negative ACK (master remains
in Master Receive state).
STOP condition (master goes to Idle state).
RECEIVE followed by STOP condition (master goes to
Idle state).
RECEIVE operation (master remains in Master Receive
state).
Illegal.
Repeated START condition followed by RECEIVE
operation with a negative ACK (master remains in Master
Receive state).
Repeated START condition followed by RECEIVE and
STOP condition (master goes to Idle state).
Repeated START condition followed by RECEIVE (master
remains in Master Receive state).
Repeated START condition followed by SEND (master
goes to Master Transmit state).
Repeated START condition followed by SEND and STOP
condition (master goes to Idle state).
NOP.
July 26, 2008
b