VG36128161BT-8H Powerchip, VG36128161BT-8H Datasheet - Page 13

• Manufacturer Part Number: VG36128161BT-8H
• Description: CMOS Synchronous Dynamic RAM
• Manufacturer: Powerchip

VIS
Note
1. All entries assume that CKE was active (High level) during the preceding clock cycle.
2. If both banks are idle, and CKE is inactive (Low level), the device will enter Power downmode.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by BankAddress(BA),
4. If both banks are idle, and CKE is inactive (Low level), the device will enter Self refresh mode.
5. Illegal if t
6. Illegal if t
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data which don’t satisfy t
10. Illegal if t
11. Illegal for single bank, but legal for other banks in multi-bank devices.
Current
Write
recovering
Write
recovering
with auto
precharge
Auto
Refreshing
Mode regis-
ter
setting
Document :1G5-0183
state of that bank.
All input buffers except CKE will be disabled.
All input buffers except CKE will be disabled.
RCD
RAS
RRD
is not satisfied.
is not satisfied.
CS
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
is not satisfied.
RAS
X
H
H
H
H
X
H
H
H
H
X
H
H
X
H
H
H
L
L
L
L
L
L
L
L
L
L
L
CAS
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
WE
X
H
H
H
H
X
H
H
H
H
X
X
X
X
X
X
H
X
X
L
L
L
L
L
L
L
L
L
X
X
X
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
X
Op - Code
X
X
X
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
X
Op - Code
X
X
X
X
X
X
X
X
X
X
Address
DPL
.
Rev.5
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
PEF/SELF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP/BST
READ/WRIT
ACT/PRE/PALL
REF/SELF/MRS ILLEGAL
DESL
NOP
BST
READ/WRITE
ACT/PRE/PALL/
REF/SELF/MRS
VG36128401B / VG36128801B / VG36128161B
Command
CMOS Synchronous Dynamic RAM
Nop
Nop
Nop
Start read, Determine AP
New write, Determine AP
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop
Nop
Nop
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop Enter idle after t
Nop Enter idle after t
ILLEGAL
ILLEGAL
Nop
Nop
ILLEGAL
ILLEGAL
ILLEGAL








Enter row active after t
Enter row active after t
Enter row active after t
Enter precharge after t
Enter precharge after t
Enter precharge after t
Enter idle after 2 Clocks
Enter idle after 2 Clocks
Action
RC
RC
Page 13
depending on the
DPL
DPL
DPL
DPL
DPL
DPL
(3/3)
3,8,11
Notes
3,11
3,11
8
3
3
3