ADP3208 ON Semiconductor, ADP3208 Datasheet - Page 30

• Manufacturer Part Number: ADP3208
• Description: 7-bit, Programmable, Dual-phase, Mobile, Cpu, Synchronous Buck Controller
• Manufacturer: ON Semiconductor

ADP3208
C
The required output decoupling for processors and platforms is
typically recommended by Intel. For systems containing both
bulk and ceramic capacitors, however, the following guidelines
can be a helpful supplement.
Select the number of ceramics and determine the total ceramic
capacitance (C
capacitors used. Keep in mind that the best location to place
ceramic capacitors is inside the socket; however, the physical
limit is twenty 0805-size pieces inside the socket. Additional
ceramic capacitors can be placed along the outer edge of the
socket. A combined ceramic capacitor value of 200 μF to 300 μF
is recommended and is usually composed of multiple 10 μF or
22 μF capacitors.
Ensure that the total amount of bulk capacitance (C
its limits. The upper limit is dependent on the VID on-the-fly
output voltage stepping (voltage step, V
of V
for load release at a given maximum load step, ΔI
version of the IMVP-6+ specification allows a maximum V
overshoot (V
step-off load current.
where
To meet the conditions of these expressions and the transient
response, the ESR of the bulk capacitor bank (R
than two times the droop resistance, R
than C
and/or the deeper sleep exit specifications and may require less
inductance or more phases. In addition, the switching frequency
may have to be increased to maintain the output ripple.
C
C
OUT
X
X
(
(
MAX
ERR
MIN
SELECTION
); the lower limit is based on meeting the critical capacitance
)
X(MAX)
k
)
≤
≥
=
n
⎛
⎜
⎜
⎜
⎜
⎜
⎝
−
×
, the system does not meet the VID on-the-fly
n
ln
k
OSMAX
×
L
2
Z
⎛
⎜
⎜
⎝
×
). This is based on the number and type of
⎛
⎜
⎜
⎝
V
R
R
V
O
) of 10 mV more than the VID voltage for a
2
ERR
O
V
×
+
L
V
⎞
⎟
⎟
⎠
V
V
VID
×
V
OSMAX
Δ
Δ
I
×
I
O
O
⎛
⎜
⎜
⎜
⎝
⎞
⎟
⎟
⎠
1
×
+
⎛
⎜
⎜
⎝
V
t
v
VID
V
V
VID
V
O
−
V
. If the C
, in time, t
C
×
Z
n
⎞
⎟
⎟
⎟
⎟
⎟
⎠
×
k
L
×
X
X(MIN)
) should be less
R
O
O
. The current
V
X
, with error
⎞
⎟
⎟
⎠
Rev. 1 | Page 30 of 38 | www.onsemi.com
) is within
2
is greater
−
1
⎞
⎟
⎟
⎟
⎠
−
CORE
(13)
(14)
C
Z
For example, if 30 pieces of 10 μF, 0805-size MLC capacitors
(C
the device exits deeper sleep, during which the V
220 mV in 22 μs with a setting error of 10 mV. If k = 3.1, solving
for the bulk capacitance yields
= 21 mF
Using six 330 μF Panasonic SP capacitors with a typical ESR of
7 mΩ each yields C
Ensure that the ESL of the bulk capacitors (L
limit the high frequency ringing during a load change. This is
tested using
where:
Q is limited to the square root of 2 to ensure a critically damped
system.
L
enough to avoid ringing during a load change. If the L
chosen bulk capacitor bank is too large, the number of ceramic
capacitors may need to be increased to prevent excessive
ringing.
For this multimode control technique, an all ceramic capacitor
design can be used if the conditions of Equations 13, 14, and 15
are satisfied.
C
C
⎛
⎜
⎜
⎜
⎝
X
X
X
Z
is about 150 pH for the six SP capacitors, which is low
1
(
(
= 300 μF) are used, the fastest VID voltage change is when
MIN
MAX
+
L
L
⎛
⎜
⎜
⎝
X
X
)
2 2
)
≥
≤
≤
≤
μs
⎛
⎜
⎜
⎜
⎜
⎜
⎜
⎝
300
C
2
2
×
Z
×
×
3
×
μF
1.
⎛
⎜
⎜
⎝
1 .
22
2
3 4
R
2
330
×
1 .
0
O
×
75
X
(
2
mV
mΩ
2
330
2 (
×
= 1.98 mF and R
1 .
nH
V
1 .
Q
mΩ
+
×
×
nH
2
mΩ
×
10
27
2
49
220
×
)
×
2
9 .
0
mV
)
3
2
×
27
nH
1 .
A
×
mV
2
9 .
×
. 1
=
⎞
⎟
⎟
⎠
×
2
4375
A
2
1 .
. 1
nH
X
4375
m
= 1.2 mΩ.
Ω
V
⎞
⎟
⎟
⎠
×
V
2
X
−
) is low enough to
−
1
300
⎞
⎟
⎟
⎟
⎠
CORE
−
300
μF
change is
X
⎞
⎟
⎟
⎟
⎟
⎟
⎟
⎠
μF
of the
=
1
0 .
(15)
mF