ADP3208 ON Semiconductor, ADP3208 Datasheet - Page 19

• Manufacturer Part Number: ADP3208
• Description: 7-bit, Programmable, Dual-phase, Mobile, Cpu, Synchronous Buck Controller
• Manufacturer: ON Semiconductor

the droop impedance of the regulator by the output current.
This value is used as the control voltage of the PWM regulator.
The droop voltage is subtracted from the DAC reference output
voltage, and the resulting voltage is used as the voltage
positioning setpoint. The arrangement results in an enhanced
feedforward response.
CURRENT CONTROL MODE AND
THERMAL BALANCE
The ADP3208 has individual inputs for monitoring the current
of each phase. The phase current information is combined with
an internal ramp to create a current-balancing feedback system
that is optimized for initial current accuracy and dynamic thermal
balance. The current balance information is independent from
the total inductor current information used for voltage positioning
described in the Active Impedance Control Mode section.
The magnitude of the internal ramp can be set so that the transient
response of the system is optimal. The ADP3208 monitors the
supply voltage to achieve feedforward control whenever the
supply voltage changes. A resistor connected from the power
input voltage rail to the RAMP pin determines the slope of the
internal PWM ramp. More detail about programming the ramp
is provided in the Application Information section.
The ADP3208 should not require external thermal balance
circuitry if a good layout is used. However, if mismatch is desired
due to uneven cooling in phase, external resistors can be added
to individually control phase currents as long as the phase currents
are mismatched by less than 30%. If unwanted mismatch exceeds
30%, a new layout that improves phase symmetry should be
considered.
In 2-phase operation, alternate cycles of the internal ramp control
the duty cycle of the separate phases. Figure 26 shows the
addition of two resistors from each switch node to the RAMP
pin; this modifies the ramp-charging current individually for
each phase. During Phase 1, SW Node 1 is high (practically at
the input voltage potential) and SW Node 2 is low (practically at
the ground potential). As a consequence, the RAMP pin, through
the R2 resistor, sees the tap point of a divider connected to the
input voltage, where R
lower element of the divider. During Phase 2, the voltages on
SW Node 1 and SW Node 2 switch and the resistors swap
VDC
Figure 26. Optional Current Balance Resistors
C
R1
20
SW1
RAMP
RESERVED FOR THERMAL BALANCE TUNE
R2
is the upper element and R
ADP3208
R
R
SW1
SW2
SWITCH NODE 1
SWITCH NODE 2
Rev. 1 | Page 19 of 38 | www.onsemi.com
SW2
is the
functions. Tuning R
optimally set for each phase. To increase the current for a
given phase, decrease R
VOLTAGE CONTROL MODE
A high-gain bandwidth error amplifier is used for the voltage
mode control loop. The noninverting input voltage is set via the
7-bit VID DAC. The VID codes are listed in Table 6. The
noninverting input voltage is offset by the droop voltage as a
function of current, commonly known as active voltage
positioning. The output of the error amplifier is the COMP pin,
which sets the termination voltage of the internal PWM ramps.
At the negative input, the FB pin is tied to the output sense
location using R
output voltage at the remote sensing point. The main loop
compensation is incorporated in the feedback network
connected between the FB and COMP pins.
POWER-GOOD MONITORING
The power-good comparator monitors the output voltage via
the CSREF pin. The PWRGD pin is an open-drain output that
can be pulled up through an external resistor to a voltage rail—
not necessarily the same VCC voltage rail that is running the
controller. A logic high level indicates that the output voltage is
within the voltage limits defined by a range around the VID
voltage setting. PWRGD goes low when the output voltage is
outside of this range.
Following the IMVP-6+ specification, the PWRGD range is
defined to be 300 mV less than and 200 mV greater than the
actual VID DAC output voltage. For any DAC voltage less than
300 mV, only the upper limit of the PWRGD range is
monitored. To prevent a false alarm, the power-good circuit is
masked during various system transitions, including a VID
change and entrance into or exit out of deeper sleep. The
duration of the PWRGD mask is set to approximately 130 μs by
an internal timer. If the voltage drop is greater than 200 mV
during deeper sleep entry or slow deeper sleep exit, the
duration of PWRGD masking is extended by the internal logic
circuit.
POWER-UP SEQUENCE AND SOFT START
The power-on ramp-up time of the output voltage is set with a
capacitor tied from the SS pin to GND. The capacitance on the
SS pin also determines the current limit latch-off time, as
explained in the Current Limit, Short-Circuit, and
Latch-Off Protection section. The power-up sequence,
including the soft start is illustrated in Figure 27.
In VCC UVLO or shutdown mode, the SS pin is held at zero
potential. When VCC ramps to a value greater than the upper
UVLO threshold while EN is asserted high, the ADP3208 enables
B
, a resistor for sensing and controlling the
SW1
and R
SW
for that phase.
SW2
allows the current to be
ADP3208