ADP3208 ON Semiconductor, ADP3208 Datasheet - Page 20

• Manufacturer Part Number: ADP3208
• Description: 7-bit, Programmable, Dual-phase, Mobile, Cpu, Synchronous Buck Controller
• Manufacturer: ON Semiconductor

ADP3208
the internal bias and starts a reset cycle of about 50 μs to 60 μs.
When the initial reset is complete, the chip detects the number
of phases set by the user and signals to ramp up the SS voltage.
During soft start, the external SS capacitor is charged by an internal
8 μA current source. The V
voltage up to the V
code (1.2 V according to the IMVP-6+ specification). While the
V
rise. When the SS pin voltage reaches 1.7 V, the ADP3208 immedi-
ately asserts the CLKEN signal low if the V
the power-good range defined by V
reads the VID codes provided by the CPU on the VID [0:6] input
pins. The V
VID voltage by a well-controlled soft transition slope (see the
Soft Transient section). During this transition, the SS capacitor
is quickly charged up to about a 2.9 V SS clamp level, controlled
by the SS source current, which is increased to 48 μA (typical).
The PWRGD signal is asserted after a t
3 ms to 10 ms, as specified by IMVP-6+. The power-good delay
can be programmed by the capacitor connected from the
PGDELAY pin to GND. Before the CLKEN signal is asserted
low, PGDELAY is reset to 0. Following the assertion of the
CLKEN signal, an internal source current of 2 μA starts
charging up the external capacitor on the PGDELAY pin.
Assuming that the V
good range defined by the VID DAC voltage, the PWRGD
signal is asserted high when the PGDELAY voltage reaches the
2.9 V power-good delay termination threshold.
CORE
V
SS
is regulated at the V
VCC = 5V
CORE
EN
Figure 27. Power-Up Sequence of ADP3208
voltage changes from the V
V
BOOT
BOOT
CORE
voltage level determined by a burnt-in VID
= 1.2V
BOOT
voltage has settled within the power-
CORE
voltage, the SS capacitor continues to
voltage follows the ramping SS
1.7V
CLKEN
BOOT
CPU_PWRGD
t
. In addition, the chip
CPU_PWRGD
DAC AND V
CORE
BOOT
voltage is within
voltage to the
delay of about
PWRGD
CORE
Rev. 1 | Page 20 of 38 | www.onsemi.com
If EN is taken low or VCC drops below the VCC UVLO
threshold, both the SS capacitor and the PGDELAY capacitor
are reset to ground to prepare the chip for a subsequent soft
start cycle.
SOFT TRANSIENT
The ADP3208 provides a soft transient function to reduce
inrush current during various transitions, including entrance
into and exit out of deeper sleep and the transition from V
to VID voltage. Reducing the inrush current helps decrease the
acoustic noise generated by the MLCC input capacitors and
inductors.
The soft transient feature is implemented with an ST buffer
amplifier that outputs constant sink or source current on the ST pin
that is connected to an external capacitor. The capacitor is used
to program the slew rate of V
transient. During steady-state operation, the reference inputs of
the voltage error amplifier and the ST amplifier are connected to
the VID DAC output. Consequently, the ST voltage is a buffered
version of VID DAC output. When system signals trigger a soft
transition, the reference input of the voltage error amplifier
switches from the DAC output to the ST output while the input
of the ST amplifier remains connected to the DAC. The ST
buffer input recognizes the almost instantaneous VID voltage
change and tries to track it. However, tracking is not instantaneous
because the slew rate of the buffer is limited by the source and sink
current capabilities of the ST output. Therefore, the V
slew rate is controlled. When the transient period is complete, the
reference input of the voltage amplifier reverts to the VID DAC
output to improve accuracy.
Table 5 lists the source/sink current on the ST pin for various
transitions. Charging/discharging the external capacitor on
the ST pin programs the voltage slew rate of the ST pin and
consequently of the V
capacitor results in a +10 mV/μs V
from deeper sleep and a ±3.3 mV/μs V
entry into or exit out of deeper sleep.
Table 5. Source/Sink Current of ST Pin
VID Transient
Slow Entry into
Fast Exit from
Slow Exit from
Transient from
1
* = do not care.
Deeper Sleep
Deeper Sleep
Deeper Sleep
V
BOOT
to VID
CORE
DPRSLP
High
Low
High
*
output. For example, a 390 pF ST
System Signals
CORE
voltage during a VID voltage
CORE
DPRSTP
*
*
High
*
CORE
slew rate for fast exit
1
slew rate for slow
ST Pin
Current (μA)
−2.5
+7.5
+2.5
±2.5
CORE
voltage
BOOT