IDT72V271LA15PFI IDT, Integrated Device Technology Inc, IDT72V271LA15PFI Datasheet - Page 27
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IDT72V271LA15PFI
Manufacturer Part Number
IDT72V271LA15PFI
Description
IC FIFO SS 16384X18 15NS 64QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V271LA10PFG.pdf
(27 pages)
Specifications of IDT72V271LA15PFI
Function
Synchronous
Memory Size
288K (16K x 18)
Access Time
15ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Rate
-
Other names
72V271LA15PFI
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V271LA15PFI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V271LA15PFI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
©
part is pin-for-pin compatible with the original “L” version. Some difference exist between the two versions. The following table details these differences.
NOTES:
1. WCLK and RCLK can vary independently and can be stopped. There is no restriction on operating WCLK and RCLK.
2. This is t
3. Tf is the period of the ‘selected clock’.
4. T
5. Typical I
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DIFFERENCES BETWEEN THE IDT72V261LA/72V271LA AND IDT72V261L/72V271L
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
RCLK
IDT has improved the performance of the IDT72V261/72V271 SuperSync™ FIFOs. The new versions are designated by the “LA” mark. The LA
is the cycle period of the read clock.
SKEW3
CC1
Pin #3
First Word Latency
(IDT Standard Mode)
First Word Latency
Retransmit Latency
(IDT Standard Mode)
Retransmit Latency
(FWFT Mode)
I
I
Typical I
is based on V
CC1
CC2
.
(FWFT Mode)
Item
CC1
CC
(5)
= 3.3V, t
A
= 25°C, f
DC (Don’t Care) - There is
RCLK. See note 1.
60ns
60ns
60ns
60ns
55mA
20mA
10 + 0.95*f
no restriction on WCLK and
3.3 VOLT CMOS SuperSync FIFO
16,384 x 9
32,768 x 9
S
(2)
(2)
(2)
(2)
= WCLK frequency = RCLK frequency (in MHz using TTL levels), data switching at f
+ t
+ t
+ t
+ t
IDT72V261LA
IDT72V271LA
NEW PART
REF
REF
REF
REF
S
+ 0.02*C
+ 1 T
+ 2 T
+ 1 T
+ 2 T
RCLK
RCLK
RCLK
RCLK
L
*f
(4)
(4)
(4)
(4)
S
(mA)
FS (Frequency Select)
t
t
t
t
150mA
15mA
Not Given
FWL
FWL
RTF
RTF
27
ADDENDUM
1
2
1
2
= 14*Tf
= 14*Tf
= 10*Tf
= 10*Tf
IDT72V261L
IDT72V271L
OLD PART
(3)
(3)
(3)
(3)
+ 3T
+ 4T
+ 2T
+ 3T
™
RCLK
RCLK
RCLK
RCLK
(4)
(4)
(4)
(4)
(ns)
(ns)
(ns) First word latency in the LA part is
(ns) First word latency in the LA part is
In the LA part this pin must be tied
to either V
not toggle after reset.
a fixed value, independent of the
frequency of RCLK or WCLK.
a fixed value, independent of the
frequency of RCLK or WCLK.
Retransmit latency in the LA part is
a fixed value, independent of the
frequency of RCLK or WCLK.
Retransmit latency in the LA part is
a fixed value, independent of the
frequency of RCLK or WCLK.
Active supply current
Standby current
Typical I
S
/2, C
CC1
Comments
CC
L
Current calculation
= Capacitive Load (in pF).
or GND and must
IDT72V261LA
IDT72V271LA