IDT72V275L15PFGI8 IDT, Integrated Device Technology Inc, IDT72V275L15PFGI8 Datasheet - Page 7
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IDT72V275L15PFGI8
Manufacturer Part Number
IDT72V275L15PFGI8
Description
IC FIFO SS 32768X18 15NS 64-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V275L15TF8.pdf
(25 pages)
Specifications of IDT72V275L15PFGI8
Function
Synchronous
Memory Size
589K (32K x 18)
Access Time
15ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Configuration
Dual
Density
576Kb
Access Time (max)
10ns
Word Size
18b
Organization
32Kx18
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Supply Current
60mA
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Rate
-
Lead Free Status / Rohs Status
Compliant
Other names
72V275L15PFGI8
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V275L15PFGI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
FUNCTIONAL DESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
IDT Standard mode or First Word Fall Through (FWFT) mode. The selection
of which mode will operate is determined during Master Reset, by the state of
the FWFT/SI input.
will be selected. This mode uses the Empty Flag (EF) to indicate whether or
not there are any words present in the FIFO. It also uses the Full Flag function
(FF) to indicate whether or not the FIFO has any free space for writing. In IDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (REN) and RCLK.
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs (Q
whether or not the FIFO has any free space for writing. In the FWFT mode,
the first word written to an empty FIFO goes directly to Q
edges, REN = LOW is not necessary. Subsequent words must be accessed
using the Read Enable (REN) and RCLK.
on which timing mode is in effect.
IDT STANDARD MODE
manner outlined in Table 1. To write data into to the FIFO, Write Enable (WEN)
must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (EF) will go HIGH. Subsequent writes will continue
to fill up the FIFO. The Programmable Almost-Empty flag (PAE) will go HIGH
after n + 1 words have been loaded into the FIFO, where n is the empty offset
value. The default setting for this value is stated in the footnote of Table 1. This
parameter is also user programmable. See section on Programmable Flag
Offset Loading.
operations were taking place, the Half-Full flag (HF) would toggle to LOW once
the 16,385th word for IDT72V275 and 32,769th word for IDT72V285
respectively was written into the FIFO. Continuing to write data into the FIFO
will cause the Programmable Almost-Full flag (PAF) to go LOW. Again, if no
reads are performed, the PAF will go LOW after (32,768-m) writes for the
IDT72V275 and (65,536-m) writes for the IDT72V285. The offset “m” is the full
offset value. The default setting for this value is stated in the footnote of Table 1.
This parameter is also user programmable. See section on Programmable Flag
Offset Loading.
operations. If no reads are performed after a reset, FF will go LOW after D writes
to the FIFO. D = 32,768 writes for the IDT72V275 and 65,536 for the
IDT72V285, respectively.
Subsequent read operations will cause PAF and HF to go HIGH at the
conditions described in Table 1. If further read operations occur, without write
operations, PAE will go LOW when there are n words in the FIFO, where n
is the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO, the EF will
go LOW inhibiting further read operations. REN is ignored when the FIFO is
empty.
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO
32,768 x 18 and 65,536 x 18
The IDT72V275/72V285 support two different timing modes of operation:
Various signals, both input and output signals operate differently depending
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
If one continued to write data into the FIFO, and we assumed no read
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write
If the FIFO is full, the first read operation will cause FF to go HIGH.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
n)
. It also uses Input Ready (IR) to indicate
n
after three RCLK rising
TM
7
register-buffered outputs.
7, 8 and 11.
FIRST WORD FALL THROUGH MODE (FWFT)
manner outlined in Table 2. To write data into to the FIFO, WEN must be LOW.
Data presented to the DATA IN lines will be clocked into the FIFO on subsequent
transitions of WCLK. After the first write is performed, the Output Ready (OR)
flag will go LOW. Subsequent writes will continue to fill up the FIFO. PAE will
go HIGH after n + 2 words have been loaded into the FIFO, where n is the empty
offset value. The default setting for this value is stated in the footnote of Table 2.
This parameter is also user programmable. See section on Programmable Flag
Offset Loading.
operations were taking place, the HF would toggle to LOW once the 16,386th
word for the IDT72V275 and 32,770th word for the IDT72V285, respectively
was written into the FIFO. Continuing to write data into the FIFO will cause the
PAF to go LOW. Again, if no reads are performed, the PAF will go LOW after
(32,769-m) writes for the IDT72V275 and (65,537-m) writes for the IDT72V285,
where m is the full offset value. The default setting for this value is stated in the
footnote of Table 2.
write operations. If no reads are performed after a reset, IR will go HIGH after
D writes to the FIFO. D = 32,769 writes for the IDT72V275 and 65,537 writes
for the IDT72V285, respectively. Note that the additional word in FWFT mode
is due to the capacity of the memory plus output register.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditions described in Table 2. If further read operations occur, without write
operations, the PAE will go LOW when there are n + 1 words in the FIFO, where
n is the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO, OR will go
HIGH inhibiting further read operations. REN is ignored when the FIFO is
empty.
buffered, and the IR flag output is double register-buffered.
12.
PROGRAMMING FLAG OFFSETS
72V285 has internal registers for these offsets. Default settings are stated in the
footnotes of Table 1 and Table 2. Offset values can be programmed into the FIFO
in one of two ways; serial or parallel loading method. The selection of the loading
method is done using the LD (Load) pin. During Master Reset, the state of the
LD input determines whether serial or parallel flag offset programming is
enabled. A HIGH on LD during Master Reset selects serial loading of offset
values and in addition, sets a default PAE offset value of 3FFH (a threshold
1,023 words from the empty boundary), and a default PAF offset value of 3FFH
(a threshold 1,023 words from the full boundary). A LOW on LD during Master
Reset selects parallel loading of offset values, and in addition, sets a default PAE
offset value of 07FH (a threshold 127 words from the empty boundary), and
a default PAF offset value of 07FH (a threshold 127 words from the full
boundary). See Figure 3, Offset Register Location and Default Values.
current offset values. It is only possible to read offset values via parallel read.
When configured in IDT Standard mode, the EF and FF outputs are double
Relevant timing diagrams for IDT Standard mode can be found in Figure
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
If one continued to write data into the FIFO, and we assumed no read
When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further
If the FIFO is full, the first read operation will cause the IR flag to go LOW.
When configured in FWFT mode, the OR flag output is triple register-
Relevant timing diagrams for FWFT mode can be found in Figure 9, 10 and
Full and Empty Flag offset values are user programmable. The IDT72V275/
In addition to loading offset values into the FIFO, it also possible to read the
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES