IDT72615L50J IDT, Integrated Device Technology Inc, IDT72615L50J Datasheet - Page 6

• Manufacturer Part Number: IDT72615L50J
• Description: IC FIFO BY SYNC 512X18X2 68PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72615L50J

• Function: Synchronous
• Memory Size: 18.4K (512 x 18 x 2)
• Access Time: 50ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72615L50J

FUNCTIONAL DESCRIPTION
applications. Data can be stored or retrieved from two sources simultaneously.
transferred into the I/O registers on clock edges, hence the interfaces are
synchronous. Two Dual-Port FIFO memory arrays are contained in the
SyncBiFIFO; one data buffer for each direction. Each port has its own
independent clock. Data transfers to the I/O registers are gated by the enable
signals. The transfer direction for each port is controlled independently by a
read/write signal. Individual output enable signals control whether the SyncBiFIFO
is driving the data lines of a port or whether those data lines are in a high-
impedance state. The processor connected to Port A of the BiFIFO can send
or receive messages directly to the Port B device using the 18-bit bypass path.
configuration, two SyncBiFIFOs operate in parallel. Both devices are pro-
grammed simultaneously, 18 data bits to each device. This configuration can
be extended to wider bus widths (54- to 54-bits, 72- to 72-bits, etc.) by adding
more SyncBiFIFOs to the configuration. Figure 1 shows multiple SyncBiFIFOs
configured for multiprocessor communication.
operations of the SyncBiFIFO. Thus, all Port A interface pins are inputs driven
by the controlling processor. Port B interfaces with a second processor. The
Port B control pins are inputs driven by the second processor.
RESET
with CS
pointers are set to the first location. A reset is required after power up before a
write operation can take place. The A→B and B→A FIFO Empty Flags (EF
EF
LOW after t
Programmable Almost- Full flags (PAF
After the reset, the offsets of the Almost-Empty flags and Almost- Full flags for the
A→B and B→A FIFO offset default to 8.
NOTES:
1. Upper SyncBiFIFO only is used in 18- to 18-bit configuration.
2. Control A consists of R/W
IDT72605/72615 CMOS SYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2
MICROPROCESSOR
BA
IDTs SyncBiFIFO is versatile for both multiprocessor and peripheral
The SyncBiFIFO has registers on all inputs and outputs. Data is only
The SyncBiFIFO can be used in multiples of 18-bits. In a 36- to 36-bit
The microprocessor or microcontroller connected to Port A controls all
Reset is accomplished whenever the Reset (RS) input is taken to a LOW state
) and Programmable Almost-Empty flags (PAE
A
, EN
RAM A
RSF
A
A
and EN
. The A→B and B→A FIFO Full Flags (FF
ADDR, I/0
DATA
CLK
B
A
HIGH. During reset, both internal read and write
, EN
A
, OE
CONTROL
A
LOGIC
, CS
AB
, PAF
A
, A
2
, A
BA
Figure 1. 36- to 36-bit Processor Interface Configuration
1
) will be set to HIGH after t
, A
CLOCK A
SYSTEM
0
. Control B consists of R/W
AB
, PAE
BA
CONTROL A
DATA A
CLK
AB
DATA A
CLK
CONTROL A
) will be set to
, FF
A
A
BA
SYNCBIFIFO
SYNCBIFIFO
) and
RSF
AB
IDT
IDT
,
.
B
, EN
6
CONTROL B
CONTROL B
systems because each port has a standard microprocessor control set. Port A
interfaces with microprocessor through the three address pins (A
Chip Select CS
to select one of six internal resources (Table 1).
register or be written into the FIFO (A
FIFO through the bypass path (A
and two B→A FIFO programmable flags) can be selected: the A→B FIFO
Almost-Empty flag Offset (A
(A
Almost-Full flag Offset (A
state.
BYPASS PATH
B. There are two full 18-bit bypass paths, one in each direction. During a bypass
operation, data is passed directly between the input and output registers, and
the FIFO memory is undisturbed.
is asserted to inform Port B that a bypass operation is beginning. The bypass
flag state is controlled by the Port A controls, although the BYP
synchronized to CLK
when A
(A
edge.
by the standard Port A (R/W
EN
deep FIFO. Data is held in each input register until it is read. Since the controls
PORT A INTERFACE
B
, OE
1
2
=0, A
B
The SyncBiFIFO is straightforward to use in micro-processor-based
With A
With A
Port A is disabled when CSA is deasserted and data A is in high-impedance
The bypass paths provide direct communication between Port A and Port
Port A initiates and terminates all bypass operations. The bypass flag, BYP
A
Once the SyncBiFIFO is in bypass mode, all data transfers are controlled
DATA B
DATA B
, OE
1
B
A
CLK
CLK
.
2
0
A
0
=000 or CS
B
=1), B→A FIFO Almost-Empty flag Offset (A
1
2
2
) interface pins. Each bypass path can be considered as a one word
A
=0 and A
=1, four programmable flags (two A→B FIFO programmable flags
B
B
0
=001and CS
CLOCK B
A
SYSTEM
pins. When CS
1
A
=0, A
B
is HIGH), BYP
. So, BYP
1
0
=1, A
A
determines whether data can be read out of output
is LOW. When Port A returns to normal FIFO mode
CONTROL
1
A
=0, A
, CLK
LOGIC
INDUSTRIAL TEMPERATURE RANGE
0
=1).
B
A
0
is asserted on the next rising edge of CLK
is asserted, A
=1).
0
A
=0), A→B FIFO Almost-Full flag Offset
B
, EN
0
is deasserted on the next CLK
=0), or the data can pass through the
A
, OE
CLK
DATA
ADDR, I/0
A
MICROPROCESSOR
2
) and Port B (R/W
,A
1
,A
1
=1, A
0
RAM B
and R/W
B
0
=0), B→A FIFO
2
A
2704 drw 05
B
-A
are used
B
signal is
0
, CLK
B
) and a
rising
B
B
B
,
,