IDT72V845L15PFI IDT, Integrated Device Technology Inc, IDT72V845L15PFI Datasheet - Page 13

• Manufacturer Part Number: IDT72V845L15PFI
• Description: IC FIFO SYNC 4096X18 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V845L15PFI

• Function: Asynchronous, Synchronous
• Memory Size: 72K (4K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Configuration: Quad
• Density: 144Kb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 4Kx18x2
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 60mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V845L15PFI

NOTES:
1. t
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
NOTES:
1. When t
2. The first word is available the cycle after EF goes HIGH, always.
3. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
the rising edge of WCLK and the rising edge of RCLK is less than t
The Latency Timing applies only at the Empty Boundary (EF = LOW).
SKEW1
Q
D
SKEW1
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. If the time between
WCLK
0
0
RCLK
Q
WEN
- Q
- D
REN
0
WCLK
OE
RCLK
EF
minimum specification, t
- Q
WEN
17
17
REN
OE
EF
17
t
ENS
t
ENS
Figure 8. First Data Word Latency with Single Register-Buffered EF
t
DS
Figure 7. Read Cycle Timing with Single Register-Buffered EF
FRL
(maximum) = t
D
t
0
OLZ
(first valid write)
t
t
SKEW1
ENH
t
CLKH
CLK
t
t
REF
A
+ t
t
SKEW1
OE
SKEW1
t
. When t
FRL (1)
t
CLK
NO OPERATION
, then EF may not change state until the next RCLK edge.
t
OLZ
t
D
SKEW1
SKEW1
1
t
t
REF
CLKL
t
< minimum specification, t
ENS
(1)
13
t
OE
VALID DATA
D
t
A
2
FRL
EF EF
EF EF (IDT Standard Mode)
t
REF
(maximum) = either 2*t
EF EF
EF EF (IDT Standard Mode)
t
OHZ
D
0
COMMERCIAL AND INDUSTRIAL
D
t
CLK
A
3
+ t
TEMPERATURE RANGES
SKEW1
or t
FEBRUARY 11, 2009
CLK
D
4295 drw 07
+ t
1
4295 drw 08
D
SKEW1
4
.