IDT72V3660L15PF IDT, Integrated Device Technology Inc, IDT72V3660L15PF Datasheet - Page 22

• Manufacturer Part Number: IDT72V3660L15PF
• Description: IC FIFO SS 4096X36 15NS 128-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3660L15PF

• Function: Asynchronous, Synchronous
• Memory Size: 147K (4K x 36)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3660L15PF

on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is reset to HIGH
on the LOW-to-HIGH transition of the Write Clock (WCLK). If synchronous PAE
configuration is selected, the PAE is updated on the rising edge of RCLK. See
Figure 21, Asynchronous Programmable Almost-Empty Flag Timing (IDT
Standard and FWFT Mode).
HALF-FULL FLAG ( HF )
beyond half-full sets HF LOW. The flag remains LOW until the difference between
the write and read pointers becomes less than or equal to half of the total depth
of the device; the rising RCLK edge that accomplishes this condition sets HF
HIGH.
HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 1,024 for the
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
If asynchronous PAE configuration is selected, the PAE is asserted LOW
This output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO
In IDT Standard mode, if no reads are performed after reset (MRS or PRS),
TM
22
36-BIT FIFO
IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660, 8,192
for the IDT72V3670, 16,384 for the IDT72V3680 and 32,768 for the IDT72V3690.
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 1,025 for the
IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for
the IDT72V3670, 16,385 for the IDT72V3680 and 32,769 for the IDT72V3690.
for the relevant timing information. Because HF is updated by both RCLK and
WCLK, it is considered asynchronous.
DATA OUTPUTS (Q
for 18-bit wide data or (Q
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
See Figure 22, Half-Full Flag Timing (IDT Standard and FWFT Modes),
(Q
0
-Q
35
) are data outputs for 36-bit wide data, (Q
0
-Q
n
0
)
-Q
8
) are data outputs for 9-bit wide data.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
0
OCTOBER 22, 2008
- Q
17
) are data outputs