IDT72V261LA10PF IDT, Integrated Device Technology Inc, IDT72V261LA10PF Datasheet - Page 24
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IDT72V261LA10PF
Manufacturer Part Number
IDT72V261LA10PF
Description
IC FIFO SS 8192X18 10NS 64QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V271LA10PFG.pdf
(27 pages)
Specifications of IDT72V261LA10PF
Function
Synchronous
Memory Size
144K (8K x 18)
Data Rate
100MHz
Access Time
10ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Configuration
Dual
Density
144Kb
Access Time (max)
6.5ns
Word Size
9b
Organization
16Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
100MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Supply Current
55mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V261LA10PF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V261LA10PF
Manufacturer:
SHARP
Quantity:
44
Company:
Part Number:
IDT72V261LA10PF
Manufacturer:
IDT
Quantity:
1 150
Company:
Part Number:
IDT72V261LA10PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V261LA10PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
control signals of multiple devices. Status flags can be detected from
any one device. The exceptions are the EF and FF functions in IDT
Standard mode and the IR and OR functions in FWFT mode. Because
of variations in skew between RCLK and WCLK, it is possible for EF/FF
deassertion and IR/OR assertion to vary by one cycle between FIFOs.
In IDT Standard mode, such problems can be avoided by creating
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
Word width may be increased simply by connecting together the
GATE
(1)
FIRST WORD FALL THROUGH/
DATA IN
SERIAL INPUT (FWFT/SI)
MASTER RESET (MRS)
PARTIAL RESET (PRS)
FULL FLAG/INPUT READY (FF/IR)
FULL FLAG/INPUT READY (FF/IR) #2
RETRANSMIT (RT)
m + n
PROGRAMMABLE (PAF)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
HALF-FULL FLAG (HF)
Figure 19. Block Diagram of 16,384 x 18 and 32,768 x 18 Width Expansion
D
0
- Dm
LOAD (LD)
m
#1
72V261LA
72V271LA
IDT
FIFO
#1
Dm
m
+1
- Dn
Q
0
24
n
- Qm
composite flags, that is, ANDing EF of every FIFO, and separately
ANDing FF of every FIFO. In FWFT mode, composite flags can be
created by ORing OR of every FIFO, and separately ORing IR of every
FIFO.
72V271LA devices. D0 - D8 from each device form a 18-bit wide input
bus and Q0-Q8 from each device form a 18-bit wide output bus. Any
word width can be attained by adding additional IDT72V261LA/72V271LA
devices.
Figure 21 demonstrates a width expansion using two IDT72V261LA/
72V261LA
72V271LA
FIFO
IDT
#2
READ CLOCK (RCLK)
n
READ ENABLE (REN)
OUTPUT ENABLE (OE)
EMPTY FLAG/OUTPUT READY (EF/OR) #1
EMPTY FLAG/OUTPUT READY (EF/OR) #2
PROGRAMMABLE (PAE)
Qm
+1
- Qn
COMMERCIAL AND INDUSTRIAL
m + n
TEMPERATURE RANGES
DATA OUT
JANUARY 30, 2009
4673 drw 22
GATE
(1)