IDT72V255LA10PF IDT, Integrated Device Technology Inc, IDT72V255LA10PF Datasheet - Page 11
![no-image](/images/manufacturer_photos/0/3/324/idt__integrated_device_technology_inc_sml.jpg)
IDT72V255LA10PF
Manufacturer Part Number
IDT72V255LA10PF
Description
IC FIFO SS 8192X18 10NS 64-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V255LA10TFG.pdf
(27 pages)
Specifications of IDT72V255LA10PF
Function
Synchronous
Memory Size
144K (8K x 18)
Access Time
10ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Configuration
Dual
Density
144Kb
Access Time (max)
6.5ns
Word Size
18b
Organization
8Kx18
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
100MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Supply Current
55mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Rate
-
Lead Free Status / Rohs Status
Not Compliant
Other names
72V255LA10PF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V255LA10PF
Manufacturer:
IDT
Quantity:
6
Company:
Part Number:
IDT72V255LA10PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V255LA10PF
Manufacturer:
IDT
Quantity:
20 000
Company:
Part Number:
IDT72V255LA10PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V255LA10PFG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V255LA10PFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Retransmit setup by setting OR HIGH. During this period, the internal read
pointer is set to the first location of the RAM array.
contents of the first location appear on the outputs. Since FWFT mode is
selected, the first word appears on the outputs, no LOW on REN is
necessary. Reading all subsequent words requires a LOW on REN to
enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT
Mode), for the relevant timing diagram.
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
If FWFT mode is selected, the FIFO will mark the beginning of the
When OR goes LOW, Retransmit setup is complete; at the same time, the
11
and PAF flags begin with the rising edge of RCLK that RT is setup. PAE is
synchronized to RCLK, thus on the second rising edge of RCLK after RT is
setup, the PAE flag will be updated. HF is asynchronous, thus the rising
edge of RCLK that RT is setup will update HF. PAF is synchronized to
WCLK, thus the second rising edge of WCLK that occurs t
rising edge of RCLK that RT is setup will update PAF. RT is synchronized to
RCLK.
For either IDT Standard mode or FWFT mode, updating of the PAE, HF
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
SKEW
after the