IDT72V255LA20PF IDT, Integrated Device Technology Inc, IDT72V255LA20PF Datasheet - Page 22
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IDT72V255LA20PF
Manufacturer Part Number
IDT72V255LA20PF
Description
IC FIFO SS 8192X18 20NS 64-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V255LA10TFG.pdf
(27 pages)
Specifications of IDT72V255LA20PF
Function
Synchronous
Memory Size
144K (8K x 18)
Access Time
20ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Configuration
Dual
Density
144Kb
Access Time (max)
12ns
Word Size
18b
Organization
8Kx18
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
50MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Supply Current
55mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Rate
-
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
Other names
72V255LA20PF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V255LA20PF
Manufacturer:
IDT
Quantity:
6
Company:
Part Number:
IDT72V255LA20PF
Manufacturer:
IDT
Quantity:
1 000
Company:
Part Number:
IDT72V255LA20PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V255LA20PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTE:
1. OE = LOW
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
3. t
4. PAF is asserted and updated on the rising edge of WCLK only.
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
D
Q
WCLK
RCLK
In IDT Standard mode: D = 8,192 for the IDT72V255LA and 16,384 for the IDT72V265LA.
In FWFT mode: D = 8,193 for the IDT72V255LA and 16,385 for the IDT72V265LA.
rising edge of RCLK and the rising edge of WCLK is less than t
0
WEN
0
WCLK
REN
SKEW2
PAF
- D
RCLK
- Q
WEN
REN
LD
15
LD
15
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t
t
CLKH
Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
Figure 15. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
ENS
t
CLKL
Figure 16. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
D - (m+1) words in FIFO
t
ENH
DATA IN OUTPUT
t
REGISTER
CLKH
t
CLKH
1
(2)
t
SKEW2
CLK
t
CLK
t
, then the PAF deassertion time may be delayed one extra WCLK cycle.
t
ENS
LDS
t
t
CLKL
DS
t
t
ENS
LDS
t
CLKL
OFFSET
PAE
2
22
t
PAF
t
t
t
ENH
DH
LDH
t
t
LDH
t
ENH
A
t
ENS
t
SKEW2
(3)
OFFSET
PAF
t
ENH
D - m words in FIFO
OFFSET
PAE
t
1
t
DH
t
ENH
LDH
t
t
LDH
ENH
t
A
COMMERCIAL AND INDUSTRIAL
(2)
TEMPERATURE RANGES
PAF
2
). If the time between the
OCTOBER 22, 2008
t
PAF
OFFSET
PAF
D-(m+1) words
in FIFO
4672 drw 19
4672 drw 17
4672 drw 18
(2)