IDT72V831L15PF IDT, Integrated Device Technology Inc, IDT72V831L15PF Datasheet - Page 12

• Manufacturer Part Number: IDT72V831L15PF
• Description: IC SYNC FIFO 2048X9 15NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V831L15PF

• Function: Asynchronous
• Memory Size: 18.4K (2K x 9)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Configuration: Quad
• Density: 36Kb
• Access Time (max): 10ns
• Word Size: 9b
• Organization: 2Kx9x2
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 40mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V831L15PF

NOTES:
1. m = PAF offset.
2. (256-m) words for the IDT72V801, (512-m) words the IDT72V811, (1,024-m) words for the IDT72V821, (2,048-m) words for the IDT72V831, (4,096-m) words for the IDT72V841,
3. t
4. If a write is performed on this rising edge of the Write Clock, there will be Full - (m-1) words in FIFO A (B) when PAFA (PAFB) goes LOW.
NOTES:
1. n = PAE offset.
2. t
3. If a read is performed on this rising edge of the Read Clock, there will be Empty + (n-1) words in FIFO A (B) when PAEA (PAEB) goes LOW.
(RENB1, RENB2)
(RENB1, RENB2)
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
RENA1, RENA2
RENA1, RENA2
or (8,192-m) words for the IDT72V851.
the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than t
rising edge.
the rising edge of WCLKA (WCLKB) and the rising edge of RCLKA (RCLKB) is less than t
rising edge.
SKEW2
SKEW2
(If Applicable)
(If Applicable)
is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for PAFA (PAFB) to change during that clock cycle. If the time between
is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for PAEA (PAEB) to change during that clock cycle. If the time between
(WCLKB)
(WENB2)
(WENB1)
(WENB2)
(RCLKB)
(WCLKB)
(RCLKB)
WCLKA
WENA2
(WENB1
WENA1
WENA2
WCLKA
RCLKA
WENA1
RCLKA
(PAFB)
PAEA,
PAEB
PAFA
t
CLKH
n words in FIFO
t
CLKH
t
t
SKEW2
t
ENS
t
ENS
t
ENS
ENS
t
CLKL
Full - (m+1) words in FIFO
t
CLKL
(1)
Figure 11. Programmable Empty Flag Timing
(2)
Figure 10. Programmable Full Flag Timing
t
t
ENH
ENH
t
t
ENH
ENH
t
PAE
12
(1)
(4)
SKEW2
SKEW2
, then PAFA (PAFB) may not change state until the next WCLKA (WCLKB)
t
, then PAEA (PAEB) may not change state until the next RCLKA (RCLKB)
PAF
TM
t
ENS
n+1 words in FIFO
t
Full - m words in FIFO
ENS
t
COMMERCIAL AND INDUSTRIAL
ENH
t
SKEW2
t
(3)
ENH
TEMPERATURE RANGES
(2)
(3)
OCTOBER 22, 2008
t
PAF
t
PAE
4093 drw 12
4093 drw 13