XC3S1000L-4FT256C Xilinx, Inc., XC3S1000L-4FT256C Datasheet - Page 118

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XC3S1000L-4FT256C

Manufacturer Part Number
XC3S1000L-4FT256C
Description
1000000 SYSTEM GATE 1.2 VOLT FPGA
Manufacturer
Xilinx, Inc.
Datasheet

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Spartan-3 FPGA Family: Pinout Descriptions
Table 79: Bitstream Options Affecting Spartan-3 Pins (Continued)
Setting Bitstream Generator Options
Refer to the
documentation.
118
M0
HSWAP_EN
TDI
TMS
TCK
TDO
Affected Pin
Name(s)
“BitGen” chapter
After configuration, this bitstream option either pulls M0 to
VCCAUX via a pull-up resistor, to ground via a pull-down resistor,
or allows M0 to float.
After configuration, this bitstream option either pulls HSWAP_EN
to VCCAUX via a pull-up resistor, to ground via a pull-down
resistor, or allows HSWAP_EN to float.
After configuration, this bitstream option either pulls TDI to
VCCAUX via a pull-up resistor, to ground via a pull-down resistor,
or allows TDI to float.
After configuration, this bitstream option either pulls TMS to
VCCAUX via a pull-up resistor, to ground via a pull-down resistor,
or allows TMS to float.
After configuration, this bitstream option either pulls TCK to
VCCAUX via a pull-up resistor, to ground via a pull-down resistor,
or allows TCK to float.
After configuration, this bitstream option either pulls TDO to
VCCAUX via a pull-up resistor, to ground via a pull-down resistor,
or allows TDO to float.
in the Xilinx ISE
Bitstream Generation Function
®
software
www.xilinx.com
DS099-4 (v2.5) December 4, 2009
HswapenPin •
Variable
TmsPin
Option
TdoPin
TckPin
M0Pin
TdiPin
Name
Product Specification
(default
Values
Pullup
Pulldown
Pullnone
Pullup
Pulldown
Pullnone
Pullup
Pulldown
Pullnone
Pullup
Pulldown
Pullnone
Pullup
Pulldown
Pullnone
Pullup
Pulldown
Pullnone
value)
R

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