IDT72841L15PF IDT, Integrated Device Technology Inc, IDT72841L15PF Datasheet - Page 10
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IDT72841L15PF
Manufacturer Part Number
IDT72841L15PF
Description
IC FIFO SYNC 4KX9 15NS 64QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
7200r
Datasheet
1.IDT72801L25TF8.pdf
(16 pages)
Specifications of IDT72841L15PF
Function
Asynchronous, Dual Port
Memory Size
36K (4K x 9)
Access Time
15ns
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Rate
-
Other names
72841L15PF
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NOTE:
1. When t
NOTE:
1. t
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
WCLKA (WCLKB)
WENA1 (WENB1)
WENA2 (WENB2)
When
The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW).
(RENB1, RENB2)
between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than t
WCLKA (WCLKB)
WENA1 (WENB1)
WENA2 (WENB2)
RCLKA (RCLKB)
SKEW1
(RENB1, RENB2)
RCLKA (RCLKB)
RENA1, RENA2
RENA1, RENA2
(If Applicable)
t
SKEW1
SKEW1
(QB
is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for EFA (EFB) to change during the current clock cycle. If the time
OEA (OEB)
(DB
EFA (EFB)
(QB
QA
OEA (OEB)
EFA (EFB)
DA
QA
0
< minimum specification, t
0
≥ minimum specification, t
0
0
- QB
0
0
- QA
- DB
- QB
- DA
- QA
8
8
8
)
8
8
)
8
)
t
ENS
FRL
FRL
= 2t
t
= t
ENS
t
ENS
CLK
CLK
t
+ t
+ t
DS
t
SKEW1
SKEW1V
SKEW1
t
ENH
Figure 7. First Data Word Latency Timing
t
CLKH
t
or t
OLZ
t
REF
t
A
CLK
t
OE
+ t
Figure 6. Read Cycle Timing
SKEW1
D
0
t
CLK
(First Valid Write)
NO OPERATION
TM
t
SKEW1
t
t
FRL
OLZ
t
10
REF
t
CLKL
(1)
VALID DATA
(1)
t
t
OHZ
ENS
D
SKEW1
1
t
OE
, then EFA (EFB) may not change state until the next RCLKA (RCLKB)
t
A
t
REF
D
2
COMMERCIAL AND INDUSTRIAL
D
0
t
A
TEMPERATURE RANGES
JANUARY 13, 2009
D
3
D
3034 drw 08
3034 drw 07
1