IDT72V251L15J IDT, Integrated Device Technology Inc, IDT72V251L15J Datasheet - Page 10
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IDT72V251L15J
Manufacturer Part Number
IDT72V251L15J
Description
IC FIFO SYNC 4096X18 15NS 32PLCC
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V221L15PFG.pdf
(14 pages)
Specifications of IDT72V251L15J
Function
Synchronous
Memory Size
72K (4K x 18)
Data Rate
67MHz
Access Time
15ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
32-PLCC
Configuration
Dual
Density
72Kb
Access Time (max)
10ns
Word Size
9b
Organization
8Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
PLCC
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Supply Current
20mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
32
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V251L15J
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V251L15J
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V251L15J8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V251L15JI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V251L15JI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTE:
1. Only one of the two Write Enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO.
NOTE:
1. When t
(If Applicable)
(If Applicable)
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
When
The Latency Timings apply only at the Empty Boundary (EF = LOW).
Q
D
WEN2
WCLK
WEN1
Q
RCLK
D
REN1,
REN2
0
0
WCLK
WEN2
WEN1
RCLK
REN2
t
0
0
REN1,
SKEW1
SKEW1
- Q
- D
OE LOW
FF
- Q
- D
OE
8
EF
8
8
8
≥ minimum specification, t
< minimum specification, t
t
t
LOW
ENS
ENS
t
DS
DATA IN OUTPUT REGISTER
t
t
SKEW1
ENS
DATA WRITE 1
NO WRITE
t
SKEW1
t
t
ENH
DATA IN OUTPUT REGISTER
ENH
FRL
FRL
t
ENH
maximum = t
maximum = 2t
t
t
FRL
A
t
WFF
t
CLK
(1)
REF
CLK
+ t
+ t
t
SKEW1
t
ENS
ENS
t
SKEW1
DS
Figure 9. Empty Flag Timing
Figure 8. Full Flag Timing
or t
CLK
+ t
SKEW1
t
WFF
t
t
ENH
10
ENH
t
REF
t
A
DATA READ
COMMERCIAL AND INDUSTRIAL
t
t
ENS
ENS
t
ENS
NO WRITE
t
DS
TEMPERATURE RANGES
DATA WRITE 2
t
ENH
t
A
t
t
t
ENH
ENH
SKEW1
t
SKEW1
DATA READ
t
COMMERCIAL AND INDUSTRIAL
WFF
NEXT DATA READ
t
t
ENS
ENS
TEMPERATURE RANGES
t
FFL
(1)
t
(1)
REF
(1)
OCTOBER 22, 2008
NO WRITE
4092 drw11
4092 drw10