EM6517 ETC, EM6517 Datasheet - Page 6

• Manufacturer Part Number: EM6517
• Description: 4 BIT MICROCONTROLLER
• Manufacturer: ETC

3
The EM6517-1 has two low power dissipation modes, standby and sleep. Figure 5 is a transition diagram for
these modes.
3.1 Active Mode
The active mode is the actual CPU running mode. Instructions are read from the internal ROM and executed by
the CPU. Leaving active mode via the halt instruction to go into standby mode, the Sleep bit write to go into
Sleep mode or a reset from port A to go into reset mode.
3.2 Standby Mode
Executing
EM6517-1 into standby mode. The voltage
regulator, oscillator, watchdog timer, ADC,
interrupts, SWB, timers and counters are
operating. However, the CPU stops since the
clock related to instruction execution stops.
Registers, RAM and I/O pins retain their
states prior to standby mode. A reset or an
interrupt request if enabled cancels standby.
3.3 Sleep Mode
Writing to the Sleep bit in the RegSysCntl1
register puts the EM6517-1 in sleep mode.
The oscillator stops and most functions of
the EM6517-1 are inactive. To be able to
write to the Sleep bit, the SleepEn bit in
RegSysCntl2 must first be set to "1". In
sleep mode only the voltage regulator and the reset input are active. The RAM data integrity is maintained.
Sleep mode may be canceled only by a high level of min 10µs at the Reset terminal or by the selected port A
input reset combination, if option InpResSleep in register OPTFSelPB is turned on.
Due to the cold-start characteristics of the oscillator, waking up from sleep mode may take some time to
guarantee stable oscillation. During sleep mode and the following start up the EM6517-1 is in reset state.
Waking up from sleep clears the Sleep flag but not the SleepEn bit. Inspecting the SleepEn allows to
determine if the EM6517-1 was powered up (SleepEn = "0") or woken up from sleep (SleepEn = "1").
Table 3.3.1. Internal State in Standby and Sleep Mode
© EM Microelectronic-Marin SA, 09/99, Rev. A/277
6
Operating Modes
I/O Port B and Serial Port
Voltage Level Detector
Instruction Execution
Oscillator Watchdog
Registers and Flags
Interrupt Functions
Option Registers
Timer & Counter
Logic Watchdog
Buzzer Output
Strobe Output
Input Port A
RAM Data
a
Reset Pin
Oscillator
Function
LCD
halt
instruction
FOR ENGINEERING ONLY
puts
Finishes ongoing measure, then stop
the
Retained
Retained
Retained
Standby
Stopped
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Figure 5. Mode transition diagram
Standby
instruction
Reset=1
Halt
IRQ
Reset=1
No pull-downs and inputs deactivated
Pull’s as defined in option register
Active
Reset
except if InpResSleep = "1"
Reset=0
Stopped (display off)
High Impedance,
High Impedance
Retained
Retained
Stopped
Stopped
Stopped
Stopped
Stopped
Active
Reset
Reset
Reset
Active
Sleep
Reset=1
EM6517
Sleep bit
write
Sleep