EM6517 ETC, EM6517 Datasheet - Page 10

• Manufacturer Part Number: EM6517
• Description: 4 BIT MICROCONTROLLER
• Manufacturer: ETC

5.3.2 OR -Type Reset function
If wanted, needs to be chosen with the metal 1 option settings ( MFP uses default NAND option ). Any one of the
port A inputs can trigger a reset. Following formula is applicable :
InpResPA = InpResPA[0] + InpResPA[1] + InpResPA[2] + InpResPA[3]
n = 0 to 3
i.e. ; - no reset if all InpResPA[n] = V
5.4 Digital Watchdog Timer Reset
The digital watchdog is a simple, non-programmable, 2-bit timer, that counts on each rising edge of Ck[1]. It will
generate a system reset if it is not periodically cleared. The watchdog timer function can be inhibited by
activating an inhibit digital watchdog bit (NoLogicWD) located in RegSysCntl3. At power up, and after any
system reset, the watchdog timer is activated.
If for any reason the CPU stops, then the watchdog timer can detect this situation and activate the system reset
signal. This function can be used to detect program overrun, endless loops, etc. For normal operation, the
watchdog timer must be reset periodically by software at least every 2.5 seconds (system clock = 32 KHz), or a
system reset signal is generated.
The watchdog timer is reset by writing a ‘1’ to the WDReset bit in the timer. This resets the timer to zero and
timer operation restarts immediately. When a ‘0’ is written to WDReset there is no effect. The watchdog timer
operates also in the standby mode and thus, to avoid a system reset, one should not remain in standby mode
for more than 2.5 seconds.
From a system reset state, the watchdog timer will become active after 3.5 seconds. However, if the watchdog
timer is influenced from other sources (i.e. prescaler reset), then it could become active after just 2.5 seconds. It
is therefore recommended to use the Prescaler IRQHz1 interrupt to periodically reset the watchdog every
second.
It is possible to read the current status of the watchdog timer in RegSysCntl2. After watchdog reset, the
counting sequence is (on each rising edge of CK[1]) : ‘00’, ‘01’, ‘10’, ‘11’ {WDVal1 WDVal0}. When going into
the ‘11’ state, the watchdog reset will be active within ½ second. The watchdog reset activates the system reset
which in turn resets the watchdog. If the watchdog is inhibited it’s timer is reset and therefore always reads ‘0’.
© EM Microelectronic-Marin SA, 09/99, Rev. A/277
10
InpRes1PA[n] InpRes2PA[n] InpResPA[n]
0
0
1
1
- Don’t care function on a single bit with
- Always Reset if any InpResPA[3:0] = V
its InpResPA[n] = Vss.
0
1
0
1
FOR ENGINEERING ONLY
V
PA[n]
not PA[n]
V
SS
DD
SS
.
DD
Figure 10. Input Port A Reset Structure
BIT
BIT
BIT
Input Port A Reset
Bit[3] Selection
BIT
[0]
[1]
[3]
[2]
InpRes1PA[3]
InpRes2PA[3]
Input Port A Reset
Bit[0] Selection
Input Port A Reset
Bit[1] Selection
Input Port A Reset
Bit[2] Selection
V
PA[3]
PA[3]
V
SS
DD
0
1 MUX
2
3 1 0
InpResPA[3]
EM6517
InpResPA
Input
Reset
from
Port A