EM636327Q-7 Etron Technology Inc., EM636327Q-7 Datasheet - Page 7

• Manufacturer Part Number: EM636327Q-7
• Description: 512K x 32 High Speed Synchronous Graphics DRAM(SGRAM)
• Manufacturer: Etron Technology Inc.

Preliminary
CLK
COM MAND
CAS# latency=1
t CK1 , DQ's
CAS# latency=2
t CK2 , DQ's
CAS# latency=3
t CK3 , DQ's
CLK
COM MAND
CAS# latency=1
t CK1 , DQ's
CAS# latency=2
t CK2 , DQ's
CAS# latency=3
t CK3 , DQ's
into high-impedance at the end of the burst unless other command is initiated. The burst length,
burst sequence, and CAS# latency are determined by the mode register, which is already
programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to
column 0 and continue).
(i.e. DQM latency is two clocks for output buffers). A read burst without the auto precharge function
may be interrupted by a subsequent Read or Write/Block Write command to the same bank or the
other active bank before the end of the burst length. It may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank too. The interrupt coming from the Read command can
occur on any clock cycle following a previous Read command (refer to the following figure).
from a Write/Block Write command. The DQMs must be asserted (HIGH) at least two clocks prior to
the Write/Block Write command to suppress data-out on the DQ pins. To guarantee the DQ pins
against I/O contention, a single cycle with high-impedance on the DQ pins must occur between the
last read data and the Write/Block Write command (refer to the following three figures). If the data
output of the burst read occurs at the second clock of the burst write, the DQMs must be asserted
(HIGH) at least one clock prior to the Write/Block Write command to avoid internal bus contention.
The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier
The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes
Read Interrupted by a Read
READ A
READ A
T0
T0
Burst Read Operation
READ B
T 1
T 1
NOP
DOUT A 0
DOUT A 0
DOUT A 1
DOUT A 0
DOUT A 0
DOUT B 0
T2
T2
NOP
NOP
(Burst Length = 4, CAS# Latency = 1, 2, 3)
DOUT A 1
DOUT B 0
T3
T3
NOP
DOUT A 0
DOUT A 0
NOP
DOUT A 2
DOUT B 1
(Burst Length = 4, CAS# Latency = 1, 2, 3)
7
DOUT A 1
DOUT B 0
DOUT A 3
DOUT B 1
DOUT A 2
DOUT B 2
T4
T4
NOP
NOP
DOUT A 3
DOUT B 2
T5
NOP
T5
NOP
DOUT B 1
DOUT A 2
DOUT B 3
DOUT A 3
DOUT B 2
DOUT B 3
T6
NOP
T6
NOP
EM636327
T7
T7
DOUT B 3
NOP
NOP
December
NOP
NOP
T8
T8
1998