EM636327Q-7 Etron Technology Inc., EM636327Q-7 Datasheet - Page 14

• Manufacturer Part Number: EM636327Q-7
• Description: 512K x 32 High Speed Synchronous Graphics DRAM(SGRAM)
• Manufacturer: Etron Technology Inc.

Preliminary
10 Block Write and AutoPrecharge command
11 Mode Register Set command
A0 - A 8
CA S#
RAS#
DQM
(RAS# = "H", CAS# = "L", WE# = "H", DSF = "H", BS = Bank, A9 = "H", A3-A7 = Column Address,
DQ0-DQ31 = Column Mask)
after the block write operation. Once this command is given, any subsequent command can not
occur within a time delay of {t
(RAS# = "L", CAS# = "L", WE# = "L", DSF = "L", BS, A0-A9 = Register Data)
Mode Register Set command programs the values of CAS# latency, Addressing Mode and Burst
Length in the Mode register to make SGRAM useful for a variety of different applications. The
default values of the Mode Register after power-up are undefined; therefore this command must be
issued at the power-up sequence. The state of pins A0~A8 and BS in the same cycle is the data
written to the mode register. One clock cycle is required to complete the write in the mode register
(refer to the following figure). The contents of the mode register can be changed using the same
command and the clock cycle requirements during operation as long as both banks are in the idle
state.
CKE
CS#
WE#
CLK
DSF
A 9
BS
DQ
The Block Write and AutoPrecharge command performs the precharge operation automatically
The mode register stores the data for controlling the various operating modes of SGRAM. The
Hi-Z
T0
Mode Register Set Cycle
t CK2
PrechargeAll
T 1
BPL
+ t
T2
RP
t
Mode Register
(min.)}.
Address Key
Set Command
RP
T3
14
Clock min.
T4
Any
Command
(CAS# Latency = 1, 2, 3)
T5
T6
T7
T8
EM636327
T9
December
T10
1998