AN2662 Freescale Semiconductor / Motorola, AN2662 Datasheet - Page 5

• Manufacturer Part Number: AN2662
• Description: Migrating from PowerQUICC II to PowerQUICC III
• Manufacturer: Freescale Semiconductor / Motorola

2.3 e500 Core Difference Comparison
This section contains a summary of the Book E architecture and it’s compatibility with the original version
of the PowerPC architecture as it was defined by Apple, IBM, and Motorola and implemented in the 603e
core (referred to as the AIM version of the PowerPC architecture).
The e500 core is Motorola’s 32-bit implementation of the Book E architecture.
2.3.1 Instruction Set Differences
In user-mode the e500 core executes legacy user-mode binaries and object files with the following
exceptions:
The supervisor mode instruction set defined by the AIM version of the PowerPC architecture is compatible
with the e500 with the following exceptions:
Figure 3 shows the e500 user instruction set to be a mnemonics instruction subset of the AIM instruction set
with some additional instructions to support the new APU features of the e500 architecture.
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The e500 core uses GPRs for floating point operations instead of separate floating point registers
(FPRs) used in the AIM architecture. The floating point instructions on the e500 only support single
precision operations and have different encoding from those on AIM processors. These changes are
generally handled by recompiling the source code with an e500 compiler.
The e500 architecture is a 32-bit implementation and 64-bit operation instructions are not
supported. Any 64-bit instructions force an illegal instruction exception.
External control input/output word index (eciwx and ecowx) instructions are not supported.
No string instructions are implemented in the e500 architecture. To support legacy binaries, it is
necessary to add some trap emulation code for the missing instructions.
The MMU architecture is different, and some TLB manipulation instructions have different
semantics—tlbsync, tlbivax, tlbre, tlbwe.
Instructions that support BATs and segment registers are not implemented due to the difference in
the MMU architecture of the e500. See Section 2.3.5, “Memory Management,” for more
information.
New instructions, such as rfci (Return from Critical Interrupt), bbelr/bblels (Branch Buffer Entry
Lock Reset/Branch Buffer Load Entry and Lock Set), wrtee[i] (Write MSR External Enable)
SPE APU: 196
SPFP APU: 23
Cache APU: 5
BTB APU: 2
Isel APU: 1
PM APU: 2
e500
Migrating from PowerQUICC II to PowerQUICC III
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 3. PowerPC User Instructions
Go to: www.freescale.com
PowerPC Book E: 185
AIM PPC
AIM PPC FP: 54
Core Differences
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