AN2662 Freescale Semiconductor / Motorola, AN2662 Datasheet - Page 26

• Manufacturer Part Number: AN2662
• Description: Migrating from PowerQUICC II to PowerQUICC III
• Manufacturer: Freescale Semiconductor / Motorola

New Features on PowerQUICC III
New Features on PowerQUICC III
Figure 13 illustrates the improved system performance and maximum slot capability between PCI and
PCI-X systems.
4.8 RapidIO
RapidIO is a packet-switched technology used for high speed point-to-point bus interconnect, compliant to
Rev 1.2 of the RapidIO specification. The PowerQUICC III is the first PowerQUICC family device (and the
first device to market) to incorporate an integrated 8-bit RapidIO controller. Hence, this is a completely new
functional block currently implemented only on the PowerQUICC III family of devices, and not a supported
feature on PowerQUICC II. The RapidIO specification is divided into three different specification layers:
logical, transport and physical. RapidIO networks are built around two basic system building
blocks—RapidIO endpoints and switches. RapidIO endpoints as the name suggests create and consume
RapidIO messages with the RapidIO switches simply passing packets between its different ports without
interpreting them. Figure 14 illustrates a typical RapidIO network.
The RapidIO physical specification on the PowerQUICC III has an 8 bit wide bus that uses low-voltage
differential signaling (LVDS) I/Os. Since RapidIO uses source synchronous double data rates, it can be run
at 500 MHz clock which can generate 1 Gigabit per pin pair i.e. running an 8-bit wide end-point, up to 1
Gigabit per second/per pair can be received/transmitted concurrently. In order to ensure maximum data
throughput, the RapidIO implementation on the PowerQUICC III supports four priority levels.
In the transportation specification, each RapidIO endpoint transmits 256-byte transaction packets which can
be controlled by atomic packet semaphores i.e. increment, decrement, set and clear. In addition to these
functions, RapidIO also has a messaging unit containing one inbound and one outbound data structure. Each
message, or telegram can be up to 4 Kbytes in size (i.e. a total of 16 packets at 256 bytes per packet).
Efficient system operation can be created using these telegrams to inform endpoints of a particular task to
be performed.
4.9 Programmable Interrupt Controller (PIC)
On the current version of PowerQUICC III all interrupts are routed via the programmable interrupt
controller (PIC) to the e500 core. One of the key design goals of the PIC was to ensure consistency and
maximize existing PowerQUICC software legacy by cascading the PowerQUICC II CPM interrupt
controller with that of the PowerQUICIII PIC.
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Endpoint
DRAM
Migrating from PowerQUICC II to PowerQUICC III
Port 3
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 14. A Simple RapidIO Network
Endpoint
Endpoint
Switch
Port 2
Port 0
CPU
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Port 1
Port 3
Endpoint
Endpoint
Switch
Port 2
Port 0
Port 1
Endpoint
ROM
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