AN2662 Freescale Semiconductor / Motorola, AN2662 Datasheet - Page 29

• Manufacturer Part Number: AN2662
• Description: Migrating from PowerQUICC II to PowerQUICC III
• Manufacturer: Freescale Semiconductor / Motorola

Initialization, Reset and Boot Procedures
Initialization, Reset and Boot Procedures
As a number of input pins are required to correctly set up the configuration of the PowerQUICC III, a
number of read-only status registers called the Global Utility registers have been added into the core. Using
these registers, users can check whether the device has been successfully configured. For example, the
PORPLLSR (POR PLL ratio status register), when read, details how the e500 core and CCB (platform)
clock ratios have been configured coming out of the POR configuration cycles. This register along with the
PORBMSR (POR boot mode status register), PORIMPSCR (POR I/O impedance status and control
register), PORDEVSR (POR debug mode status register), PORDBGMSR (POR debug mode status register)
and the GPPORCR (general-purpose POR configuration register), provide a useful toolset for debugging
hardware initialization.
5.2 System Reset Differences
At reset, things are different on the PowerQUICC III when compared against the PowerQUICC II. First, the
time at which the PowerQUICC III is brought out of reset can either be controlled in the normal manner i.e.
during initial power-up, or it can be controlled as an agent from either the PCI or RapidIO interface.
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HRESET_REQ
1
POR Configs
•
•
•
Multiplexed with TRIG_OUT.
PLL Configs
HRESET
SRESET
SYSCLK
TRESET
ASLEEP
READY
e500 boot—if configured.
initialization/activation via the PCI/RapidIO—if active.
Pre configuration of the PowerQUICC III performed by the I2C boot sequencer.
1
Migrating from PowerQUICC II to PowerQUICC III
Freescale Semiconductor, Inc.
For More Information On This Product,
(high impedance)
(High Impedance)
(High Impedance)
Figure 16. POR Configuration Cycles
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