AN2662 Freescale Semiconductor / Motorola, AN2662 Datasheet - Page 16

• Manufacturer Part Number: AN2662
• Description: Migrating from PowerQUICC II to PowerQUICC III
• Manufacturer: Freescale Semiconductor / Motorola

New Features on PowerQUICC III
New Features on PowerQUICC III
The implementation of the ECM is such that transactions across it are not implicitly coherent. The internal
bus is snooped by e500 L1 and L2 caches to maintain coherency only if the transaction across the ECM has
the GBL bit set to mark it as a global transaction. If this is not the case then the ECM is used as a simple
conduit for the transaction to get to its destination. Thus, only global transactions across the ECM are
coherent transactions; all others (between the CPM and the local bus, and across the on-chip fabric) are
non-coherent. In reality, the majority of all internal data transfers are in some way processed by the ECM.
Inside the PowerQUICC III is a 32-bit local address mapping unit than allows 32-bit addressing structures
to map to larger addressable devices completely independently, for example, 32-bit PowerQUICC III
address to 64-bit PCI address. As a result, the PowerQUICC III system map normally consists of a 32-bit
local address space and a larger external address space. Accessing external address space is achieved by
using inbound and outbound translation windows, whereas inbound transactions use local access windows
(LAWs). It is through these LAWS that the ECM knows where/how to route transactions throughout the
internal PowerQUICC III architecture. Only transactions that hit a particular IBW or LAW are actually
processed.
In Figure 7, four different address mapping examples are shown:
The coherency module has been optimized for low-latency access to the DDR memory by performing
‘speculative reads’ using a separate internal bus to the DDR controller. This speculative read starts a
transaction in the DDR memory before a response from the cache is received on whether the access is
16
RapidIO 2
1. PCI to local bus transaction: inbound window (IBW) to local address window (LAW) that the ECM
2. PCI to DDR transaction: inbound window (IBW) on PCI space to local address window (LAW)
3. CPU e500 to RapidIO: direct from CPU local address window (LAW) which the ECM then routes
4. PCI to RapidIO: from PCI space inbound window (IBW) direct to RapidIO outbound window
PCI to
PCI to
PCI to
DDR
2
LB
then routes to the local bus.
for DDR. In this example the transaction comes through OCeaN by way of the ECM block and on
to the DDR.
to the RapidIO outbound window (OBW) for the RapidIO device.
(OBW) for the RapidIO device. Here the ECM is not involved, the transaction is simply a OCeaN
Port-to-Port transaction, local to the OCeaN block.
64
– 1
0
PCI Map
IBW
IBW
IBW
Migrating from PowerQUICC II to PowerQUICC III
Freescale Semiconductor, Inc.
For More Information On This Product,
RapidIO 1
Figure 7. Address Mapping Example
CPU to
2
32
Go to: www.freescale.com
– 1
0
LAW (DDR)
Local Map
LAW
LAW
Local
Bus
2
34
– 1
0
RapidIO Map
OBW
OBW
OBW
MOTOROLA
RapidIO
Device 1
RapidIO
Device 2