CY2SSTV8575 Cypress Semiconductor, CY2SSTV8575 Datasheet - Page 6

• Manufacturer Part Number: CY2SSTV8575
• Description: Differential Clock Buffer/Driver
• Manufacturer: Cypress Semiconductor

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AC Input Parameters
AC Output Parameters
Notes:
Document #: 38-07458 Rev. **
5.
6.
7.
8.
9.
F
D
F
t
D
T
T
t
T
T
T
T
T
T
T
Parameter
Parameter
LOCK
SKEW
in
OR
R
F
PLH
PHL
ODIS
OENB
JIT(CC)
PHASE
JIT(PHASE)
TYC
TYC
Parameters are guaranteed by design and characterization. Not 100% tested in production.
PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 50 kHz with a down
spread of –0.5%.
While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = t
where the cycle time (t
Refers to transition of non-inverting output.
All differential input and output terminals are terminated with 120 /16 pF as shown in Figure 2.
Input Frequency
Input Duty Cycle
Output frequency range
Maximum PLL Lock Time
Duty Cycle
Rise Time
Fall Time
Any Output to Any Output Skew
Propagation Delay (Low to High)
Propagation Delay (High to Low)
Output Disable Time
Output Enable Time
Cycle to Cycle Jitter
Phase Error
Phase Error Jitter
C
) decreases as the frequency goes up.
Description
Description
[7]
(AV
(AVDD= VDDQ = 2.5 ±5%, Temperature = 0°C to +85°C)
DD
[8]
= VDDQ = 2.5 ±5%, T
[8]
[9]
AV
20% to 80% of V
CLK to Y
1.25
AV
AV
60 MHz to 100 MHz
101 MHz to 170 MHz
20% to 80% of V
All outputs equally loaded
CLK to Y
All outputs
All outputs
All outputs @ 66 MHz
All outputs @ 66 MHz
DD
DD
DD
, V
, V
, V
A
= 0°C to +85°C)
DD
DD
DD
= 2.5V±0.2V
= 2.5V±0.2V
= 2.5V±0.2V
Conditions
Conditions
OD
OD
[5,6]
–100
–150
Min.
Min.
49.5
–50
1.5
1.5
60
40
60
49
–
1
1
–
–
–
Typ.
Typ.
3.5
3.5
50
–
–
–
–
–
–
–
–
3
3
–
–
–
CY2SSTV8575
Max.
Max.
–100
50.5
170
170
100
100
150
60
51
50
2
2
6
6
–
–
Page 6 of 8
Unit
MHz
Unit
MHz
V/ns
V/ns
ps
ns
ns
ns
ns
ps
ps
ps
%
%
%
WH
S
/t
C
,