CY2SSTV8575 Cypress Semiconductor, CY2SSTV8575 Datasheet - Page 3

• Manufacturer Part Number: CY2SSTV8575
• Description: Differential Clock Buffer/Driver
• Manufacturer: Cypress Semiconductor

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Power Management Functions
Output enable/disable control of the CY2SSTV8575 allows the
user to implement power management schemes into the de-
sign. Outputs are three-stated/disabled when OE is asserted
low, see Table 1. The enabling and disabling of outputs is done
in such a manner to eliminate the possibility of the partial “runt”
clocks.
Zero Delay Buffer
When used as a zero delay buffer the CY2SSTV8575 will likely
be in a nested clock tree application. For these applications
the CY2SSTV8575 offers a differential clock input pair as a
Note:
Document #: 38-07458 Rev. **
1.
Output load capacitance for 2 DDR-SDRAM loads: 5 pF < CL < 8 pF.
CLK#
CLK
represents a capacitive
DDR _SDRAM
load
120 Ohm
120 Ohm
PLL
FBIN
FBIN#
Figure 1. Clock Structure 1
FBOUT#
FBOUT
Yx#
Yx
PLL reference. The CY2SSTV8575 can lock onto the refer-
ence and translate with near zero delay to low-skew outputs.
For normal operation, the external feedback input, FBIN, is
connected to the feedback output, FBOUT. By connecting the
feedback output to the feedback input the propagation delay
through the device is eliminated. The PLL works to align the
output edge with tine input reference edge thus producing a
near zero delay. The reference frequency affects the static
phase offset of the PLL and thus the relative delay between
the inputs and outputs.
When AVDD is strapped LOW, the PLL is turned off and by-
passed for test purposes.
= 2.5"
0.3"
[1]
= 0.6" (Split to Terminator)
SDRAM
SDRAM
DDR -
DDR -
VCP
VTR
CY2SSTV8575
120 Ohm
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