CY2SSTV8575 Cypress Semiconductor, CY2SSTV8575 Datasheet - Page 2

• Manufacturer Part Number: CY2SSTV8575
• Description: Differential Clock Buffer/Driver
• Manufacturer: Cypress Semiconductor

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Pin Description
Table 1. Function Table
Document #: 38-07458 Rev. **
5,6
21
22
2,12,15,27,30
1,11,16,28,31
18
19
23
3,4,7,13,20,26,
29
8
10,14,17,24,25,
32
9
AVDD
GND
GND
2.5V
2.5V
2.5V
X
X
Pin
OE
H
H
H
H
H
L
L
CLK, CLK#
FBIN#
FBIN
Y(0:4)
Y(0:4)#
FBOUT
FBOUT#
OE
VDDQ
AVDD
VSS
AVSS
Name
INPUTS
< 20 MHz
CLK
H
H
H
L
L
L
I/O
O
O
O
O
I
I
I
I
LV Differential Input
Differential Input
Differential Outputs
Differential Outputs
2.5V Nominal
2.5V Nominal
0.0V Ground
0.0V Analog Ground
< 20 MHz
CLK#
H
H
H
L
L
L
Type
Hi-Z
Y
H
Z
Z
H
L
L
Differential Clock Input
Feedback Clock Input. Connect to FBOUT# for accessing the
PLL.
Feedback Clock Input. Connect to FBOUT for accessing the
PLL.
Clock + Outputs
Clock – Outputs
Feedback Clock Output. Connect to FBIN for normal
operation. A bypass delay capacitor at this output will control
Input Reference/Output Clocks phase relationships.
Feedback Clock Output. Connect to FBIN# for normal
operation. A bypass delay capacitor at this output will control
Input Reference/Output Clocks phase relationships.
Output Enable Input. When OE is set HIGH, all Q and Q#
outputs are enabled and switch at the same frequency as CLK.
When set LOW, all Q and Q# outputs are disabled (Hi-Z) and
the PLL is powered down.
2.5V Power Supply for Output Clock Buffers
2.5V Power Supply for PLL. When AVDD is at GND, PLL is
bypassed and CLK is buffered directly to the device outputs.
During disable (OE = 0), the PLL is powered down.
Common Ground
Analog Ground
Hi-Z
Y#
H
Z
Z
H
L
L
OUTPUTS
FBOUT
Hi-Z
H
Z
Z
H
L
L
Description
FBOUT#
HI-Z
H
H
Z
Z
L
L
CY2SSTV8575
BYPASSED/OFF
BYPASSED/OFF
OFF
PLL
On
On
Off
Off
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